[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

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git-clang-format --diff e26d9070d3eaee587b3ef0da6d12200a5b994765 75a57397bb645eb41035d33a56381cb65c8bc0bc --extensions h,cpp,c -- clang/lib/Basic/Targets/RISCV.cpp clang/test/CodeGen/RISCV/riscv-inline-asm.c llvm/lib/CodeGen/ValueTypes.cpp llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h llvm/lib/Target/RISCV/RISCVSubtarget.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b53f3a1b71..9fdf0cb59e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6423,10 +6423,12 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       std::tie(Lo, Hi) = DAG.SplitScalar(Op0, DL, MVT::i32, MVT::i32);
       return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
     }
-    if (VT == Subtarget.getXLenPairVT() && Op0VT.isScalarInteger() && Op0VT.getSizeInBits() == 2 * Subtarget.getXLen()) {
+    if (VT == Subtarget.getXLenPairVT() && Op0VT.isScalarInteger() &&
+        Op0VT.getSizeInBits() == 2 * Subtarget.getXLen()) {
       SDValue Lo, Hi;
       std::tie(Lo, Hi) = DAG.SplitScalar(Op0, DL, XLenVT, XLenVT);
-      return DAG.getNode(RISCVISD::BuildPairGPR, DL, Subtarget.getXLenPairVT(), Lo, Hi);
+      return DAG.getNode(RISCVISD::BuildPairGPR, DL, Subtarget.getXLenPairVT(),
+                         Lo, Hi);
     }
 
     // Consider other scalar<->scalar casts as legal if the types are legal.
@@ -12869,9 +12871,13 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
       SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
                                    NewReg.getValue(0), NewReg.getValue(1));
       Results.push_back(RetReg);
-    } else if (VT.isInteger() && VT.getSizeInBits() == 2 * Subtarget.getXLen() && Op0VT == Subtarget.getXLenPairVT()) {
-      SDValue NewReg = DAG.getNode(RISCVISD::SplitPairGPR, DL, DAG.getVTList(XLenVT, XLenVT), Op0);
-      SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, VT, NewReg.getValue(0), NewReg.getValue(1));
+    } else if (VT.isInteger() &&
+               VT.getSizeInBits() == 2 * Subtarget.getXLen() &&
+               Op0VT == Subtarget.getXLenPairVT()) {
+      SDValue NewReg = DAG.getNode(RISCVISD::SplitPairGPR, DL,
+                                   DAG.getVTList(XLenVT, XLenVT), Op0);
+      SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, VT, NewReg.getValue(0),
+                                   NewReg.getValue(1));
       Results.push_back(RetReg);
     } else if (!VT.isVector() && Op0VT.isFixedLengthVector() &&
                isTypeLegal(Op0VT)) {

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https://github.com/llvm/llvm-project/pull/112983