[llvm] Refine TableGen code to comply with `clang-tidy` checks and remove unused imports (PR #113318)

via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 22 07:00:48 PDT 2024


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Jerry Sun (jerryyiransun)

<details>
<summary>Changes</summary>



---

Patch is 124.11 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113318.diff


23 Files Affected:

- (modified) llvm/utils/TableGen/ARMTargetDefEmitter.cpp (+10-10) 
- (modified) llvm/utils/TableGen/Attributes.cpp (-1) 
- (modified) llvm/utils/TableGen/CTagsEmitter.cpp (-1) 
- (modified) llvm/utils/TableGen/CallingConvEmitter.cpp (+24-24) 
- (modified) llvm/utils/TableGen/CodeEmitterGen.cpp (+116-116) 
- (modified) llvm/utils/TableGen/CodeGenMapTable.cpp (+26-26) 
- (modified) llvm/utils/TableGen/DAGISelEmitter.cpp (+4-4) 
- (modified) llvm/utils/TableGen/DFAPacketizerEmitter.cpp (+15-15) 
- (modified) llvm/utils/TableGen/DXILEmitter.cpp (+21-22) 
- (modified) llvm/utils/TableGen/DirectiveEmitter.cpp (+117-117) 
- (modified) llvm/utils/TableGen/DisassemblerEmitter.cpp (+2-2) 
- (modified) llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp (-2) 
- (modified) llvm/utils/TableGen/GlobalISelEmitter.cpp (-1) 
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (-1) 
- (modified) llvm/utils/TableGen/IntrinsicEmitter.cpp (-1) 
- (modified) llvm/utils/TableGen/OptionParserEmitter.cpp (+13-14) 
- (modified) llvm/utils/TableGen/OptionRSTEmitter.cpp (+2-2) 
- (modified) llvm/utils/TableGen/PseudoLoweringEmitter.cpp (-1) 
- (modified) llvm/utils/TableGen/RISCVTargetDefEmitter.cpp (+2-2) 
- (modified) llvm/utils/TableGen/SubtargetEmitter.cpp (+133-133) 
- (modified) llvm/utils/TableGen/TableGen.cpp (+6-6) 
- (modified) llvm/utils/TableGen/VTEmitter.cpp (+2-3) 
- (modified) llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp (-1) 


``````````diff
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 6b8ebf96cdf383..fe8a82e6d7e617 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -25,19 +25,19 @@
 using namespace llvm;
 
 /// Collect the full set of implied features for a SubtargetFeature.
-static void CollectImpliedFeatures(std::set<const Record *> &SeenFeats,
+static void collectImpliedFeatures(std::set<const Record *> &SeenFeats,
                                    const Record *Rec) {
   assert(Rec->isSubClassOf("SubtargetFeature") &&
          "Rec is not a SubtargetFeature");
 
   SeenFeats.insert(Rec);
   for (const Record *Implied : Rec->getValueAsListOfDefs("Implies"))
-    CollectImpliedFeatures(SeenFeats, Implied);
+    collectImpliedFeatures(SeenFeats, Implied);
 }
 
-static void CheckFeatureTree(const Record *Root) {
+static void checkFeatureTree(const Record *Root) {
   std::set<const Record *> SeenFeats;
-  CollectImpliedFeatures(SeenFeats, Root);
+  collectImpliedFeatures(SeenFeats, Root);
 
   // Check that each of the mandatory (implied) features which is an
   // ExtensionWithMArch is also enabled by default.
@@ -53,12 +53,12 @@ static void CheckFeatureTree(const Record *Root) {
   }
 }
 
-static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
+static void emitArmTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
   OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
 
   // Look through all SubtargetFeature defs with the given FieldName, and
   // collect the set of all Values that that FieldName is set to.
-  auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
+  auto GatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
     llvm::StringSet<> Set;
     for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
       if (Rec->getValueAsString("FieldName") == FieldName) {
@@ -88,7 +88,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
      << "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
      << "#endif\n\n";
   const StringSet<> ARMProcFamilyVals =
-      gatherSubtargetFeatureFieldValues("ARMProcFamily");
+      GatherSubtargetFeatureFieldValues("ARMProcFamily");
   for (const StringRef &Family : ARMProcFamilyVals.keys())
     OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
   OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
@@ -97,7 +97,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
      << "#define ARM_ARCHITECTURE(ENUM)\n"
      << "#endif\n\n";
   // This should correspond to instances of the Architecture tablegen class.
-  const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
+  const StringSet<> ARMArchVals = GatherSubtargetFeatureFieldValues("ARMArch");
   for (const StringRef &Arch : ARMArchVals.keys())
     OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
   OS << "\n#undef ARM_ARCHITECTURE\n\n";
@@ -315,7 +315,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
     auto Profile = Arch->getValueAsString("Profile");
     auto ArchInfo = ArchInfoName(Major, Minor, Profile);
 
-    CheckFeatureTree(Arch);
+    checkFeatureTree(Arch);
 
     OS << "  {\n"
        << "    \"" << Name << "\",\n"
@@ -343,5 +343,5 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
 }
 
 static TableGen::Emitter::Opt
-    X("gen-arm-target-def", EmitARMTargetDef,
+    X("gen-arm-target-def", emitArmTargetDef,
       "Generate the ARM or AArch64 Architecture information header.");
diff --git a/llvm/utils/TableGen/Attributes.cpp b/llvm/utils/TableGen/Attributes.cpp
index ed00debc398cb9..652dd31a9adb27 100644
--- a/llvm/utils/TableGen/Attributes.cpp
+++ b/llvm/utils/TableGen/Attributes.cpp
@@ -9,7 +9,6 @@
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
-#include <vector>
 using namespace llvm;
 
 #define DEBUG_TYPE "attr-enum"
diff --git a/llvm/utils/TableGen/CTagsEmitter.cpp b/llvm/utils/TableGen/CTagsEmitter.cpp
index 3718486ff7ad4e..8c347456eb8940 100644
--- a/llvm/utils/TableGen/CTagsEmitter.cpp
+++ b/llvm/utils/TableGen/CTagsEmitter.cpp
@@ -17,7 +17,6 @@
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
-#include <algorithm>
 #include <vector>
 using namespace llvm;
 
diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp
index fefc407c354a5d..e44b13f0436313 100644
--- a/llvm/utils/TableGen/CallingConvEmitter.cpp
+++ b/llvm/utils/TableGen/CallingConvEmitter.cpp
@@ -34,12 +34,12 @@ class CallingConvEmitter {
 public:
   explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {}
 
-  void run(raw_ostream &o);
+  void run(raw_ostream &O);
 
 private:
-  void EmitCallingConv(const Record *CC, raw_ostream &O);
-  void EmitAction(const Record *Action, indent Indent, raw_ostream &O);
-  void EmitArgRegisterLists(raw_ostream &O);
+  void emitCallingConv(const Record *CC, raw_ostream &O);
+  void emitAction(const Record *Action, indent Indent, raw_ostream &O);
+  void emitArgRegisterLists(raw_ostream &O);
 };
 } // End anonymous namespace
 
@@ -74,16 +74,16 @@ void CallingConvEmitter::run(raw_ostream &O) {
   Records.startTimer("Emit full descriptions");
   for (const Record *CC : CCs) {
     if (!CC->getValueAsBit("Custom")) {
-      EmitCallingConv(CC, O);
+      emitCallingConv(CC, O);
     }
   }
 
-  EmitArgRegisterLists(O);
+  emitArgRegisterLists(O);
 
   O << "\n#endif // CC_REGISTER_LIST\n";
 }
 
-void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
+void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) {
   const ListInit *CCActions = CC->getValueAsListInit("Actions");
   Counter = 0;
 
@@ -106,8 +106,8 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
     << std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
     << std::string(Pad, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n";
   // Emit all of the actions, in order.
-  for (unsigned i = 0, e = CCActions->size(); i != e; ++i) {
-    const Record *Action = CCActions->getElementAsRecord(i);
+  for (unsigned I = 0, E = CCActions->size(); I != E; ++I) {
+    const Record *Action = CCActions->getElementAsRecord(I);
     SwiftAction =
         llvm::any_of(Action->getSuperClasses(),
                      [](const std::pair<const Record *, SMRange> &Class) {
@@ -116,23 +116,23 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
                      });
 
     O << "\n";
-    EmitAction(Action, indent(2), O);
+    emitAction(Action, indent(2), O);
   }
 
   O << "\n  return true; // CC didn't match.\n";
   O << "}\n";
 }
 
-void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
+void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
                                     raw_ostream &O) {
   if (Action->isSubClassOf("CCPredicateAction")) {
     O << Indent << "if (";
 
     if (Action->isSubClassOf("CCIfType")) {
       const ListInit *VTs = Action->getValueAsListInit("VTs");
-      for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
-        const Record *VT = VTs->getElementAsRecord(i);
-        if (i != 0)
+      for (unsigned I = 0, E = VTs->size(); I != E; ++I) {
+        const Record *VT = VTs->getElementAsRecord(I);
+        if (I != 0)
           O << " ||\n    " << Indent;
         O << "LocVT == " << getEnumName(getValueType(VT));
       }
@@ -145,7 +145,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
     }
 
     O << ") {\n";
-    EmitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
+    emitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
     O << Indent << "}\n";
   } else {
     if (Action->isSubClassOf("CCDelegateTo")) {
@@ -170,8 +170,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
           << "[] = {\n";
         O << Indent << "  ";
         ListSeparator LS;
-        for (unsigned i = 0, e = RegList->size(); i != e; ++i) {
-          std::string Name = getQualifiedName(RegList->getElementAsRecord(i));
+        for (unsigned I = 0, E = RegList->size(); I != E; ++I) {
+          std::string Name = getQualifiedName(RegList->getElementAsRecord(I));
           if (SwiftAction)
             AssignedSwiftRegsMap[CurrentAction].insert(Name);
           else
@@ -229,16 +229,16 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
           << "[] = {\n";
         O << Indent << "  ";
         ListSeparator LS;
-        for (unsigned i = 0, e = RegList->size(); i != e; ++i)
-          O << LS << getQualifiedName(RegList->getElementAsRecord(i));
+        for (unsigned I = 0, E = RegList->size(); I != E; ++I)
+          O << LS << getQualifiedName(RegList->getElementAsRecord(I));
         O << "\n" << Indent << "};\n";
 
         O << Indent << "static const MCPhysReg RegList" << ShadowRegListNumber
           << "[] = {\n";
         O << Indent << "  ";
         ListSeparator LSS;
-        for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
-          O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+        for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+          O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
         O << "\n" << Indent << "};\n";
 
         O << Indent << "if (MCRegister Reg = State.AllocateReg(RegList"
@@ -286,8 +286,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
         << ShadowRegListNumber << "[] = {\n";
       O << Indent << "  ";
       ListSeparator LS;
-      for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
-        O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+      for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+        O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
       O << "\n" << Indent << "};\n";
 
       O << Indent << "int64_t Offset" << ++Counter << " = State.AllocateStack("
@@ -356,7 +356,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
   }
 }
 
-void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) {
+void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) {
   // Transitively merge all delegated CCs into AssignedRegsMap.
   using EntryTy = std::pair<std::string, std::set<std::string>>;
   bool Redo;
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 4d356774f98dcc..74c105986104da 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -52,10 +52,10 @@ class CodeEmitterGen {
 public:
   CodeEmitterGen(const RecordKeeper &R) : Records(R) {}
 
-  void run(raw_ostream &o);
+  void run(raw_ostream &O);
 
 private:
-  int getVariableBit(const std::string &VarName, const BitsInit *BI, int bit);
+  int getVariableBit(const std::string &VarName, const BitsInit *BI, int Bit);
   std::pair<std::string, std::string>
   getInstructionCases(const Record *R, const CodeGenTarget &Target);
   void addInstructionCasesForEncoding(const Record *R,
@@ -69,10 +69,10 @@ class CodeEmitterGen {
                                const CodeGenTarget &Target);
 
   void emitInstructionBaseValues(
-      raw_ostream &o, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
+      raw_ostream &O, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
       const CodeGenTarget &Target, unsigned HwMode = DefaultMode);
   void
-  emitCaseMap(raw_ostream &o,
+  emitCaseMap(raw_ostream &O,
               const std::map<std::string, std::vector<std::string>> &CaseMap);
   unsigned BitWidth = 0u;
   bool UseAPInt = false;
@@ -81,12 +81,12 @@ class CodeEmitterGen {
 // If the VarBitInit at position 'bit' matches the specified variable then
 // return the variable bit position.  Otherwise return -1.
 int CodeEmitterGen::getVariableBit(const std::string &VarName,
-                                   const BitsInit *BI, int bit) {
-  if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
+                                   const BitsInit *BI, int Bit) {
+  if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(Bit))) {
     if (const VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
       if (VI->getName() == VarName)
         return VBI->getBitNum();
-  } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
+  } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(Bit))) {
     if (VI->getName() == VarName)
       return 0;
   }
@@ -104,19 +104,19 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
   CodeGenInstruction &CGI = Target.getInstruction(R);
 
   // Determine if VarName actually contributes to the Inst encoding.
-  int bit = BI->getNumBits() - 1;
+  int Bit = BI->getNumBits() - 1;
 
   // Scan for a bit that this contributed to.
-  for (; bit >= 0;) {
-    if (getVariableBit(VarName, BI, bit) != -1)
+  for (; Bit >= 0;) {
+    if (getVariableBit(VarName, BI, Bit) != -1)
       break;
 
-    --bit;
+    --Bit;
   }
 
   // If we found no bits, ignore this value, otherwise emit the call to get the
   // operand encoding.
-  if (bit < 0)
+  if (Bit < 0)
     return true;
 
   // If the operand matches by name, reference according to that
@@ -175,97 +175,97 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
   // Precalculate the number of lits this variable contributes to in the
   // operand. If there is a single lit (consecutive range of bits) we can use a
   // destructive sequence on APInt that reduces memory allocations.
-  int numOperandLits = 0;
-  for (int tmpBit = bit; tmpBit >= 0;) {
-    int varBit = getVariableBit(VarName, BI, tmpBit);
+  int NumOperandLits = 0;
+  for (int TmpBit = Bit; TmpBit >= 0;) {
+    int VarBit = getVariableBit(VarName, BI, TmpBit);
 
     // If this bit isn't from a variable, skip it.
-    if (varBit == -1) {
-      --tmpBit;
+    if (VarBit == -1) {
+      --TmpBit;
       continue;
     }
 
     // Figure out the consecutive range of bits covered by this operand, in
     // order to generate better encoding code.
-    int beginVarBit = varBit;
+    int BeginVarBit = VarBit;
     int N = 1;
-    for (--tmpBit; tmpBit >= 0;) {
-      varBit = getVariableBit(VarName, BI, tmpBit);
-      if (varBit == -1 || varBit != (beginVarBit - N))
+    for (--TmpBit; TmpBit >= 0;) {
+      VarBit = getVariableBit(VarName, BI, TmpBit);
+      if (VarBit == -1 || VarBit != (BeginVarBit - N))
         break;
       ++N;
-      --tmpBit;
+      --TmpBit;
     }
-    ++numOperandLits;
+    ++NumOperandLits;
   }
 
   unsigned BitOffset = -1;
-  for (; bit >= 0;) {
-    int varBit = getVariableBit(VarName, BI, bit);
+  for (; Bit >= 0;) {
+    int VarBit = getVariableBit(VarName, BI, Bit);
 
     // If this bit isn't from a variable, skip it.
-    if (varBit == -1) {
-      --bit;
+    if (VarBit == -1) {
+      --Bit;
       continue;
     }
 
     // Figure out the consecutive range of bits covered by this operand, in
     // order to generate better encoding code.
-    int beginInstBit = bit;
-    int beginVarBit = varBit;
+    int BeginInstBit = Bit;
+    int BeginVarBit = VarBit;
     int N = 1;
-    for (--bit; bit >= 0;) {
-      varBit = getVariableBit(VarName, BI, bit);
-      if (varBit == -1 || varBit != (beginVarBit - N))
+    for (--Bit; Bit >= 0;) {
+      VarBit = getVariableBit(VarName, BI, Bit);
+      if (VarBit == -1 || VarBit != (BeginVarBit - N))
         break;
       ++N;
-      --bit;
+      --Bit;
     }
 
-    std::string maskStr;
-    int opShift;
+    std::string MaskStr;
+    int OpShift;
 
-    unsigned loBit = beginVarBit - N + 1;
-    unsigned hiBit = loBit + N;
-    unsigned loInstBit = beginInstBit - N + 1;
-    BitOffset = loInstBit;
+    unsigned LoBit = BeginVarBit - N + 1;
+    unsigned HiBit = LoBit + N;
+    unsigned LoInstBit = BeginInstBit - N + 1;
+    BitOffset = LoInstBit;
     if (UseAPInt) {
-      std::string extractStr;
+      std::string ExtractStr;
       if (N >= 64) {
-        extractStr = "op.extractBits(" + itostr(hiBit - loBit) + ", " +
-                     itostr(loBit) + ")";
-        Case += "      Value.insertBits(" + extractStr + ", " +
-                itostr(loInstBit) + ");\n";
+        ExtractStr = "op.extractBits(" + itostr(HiBit - LoBit) + ", " +
+                     itostr(LoBit) + ")";
+        Case += "      Value.insertBits(" + ExtractStr + ", " +
+                itostr(LoInstBit) + ");\n";
       } else {
-        extractStr = "op.extractBitsAsZExtValue(" + itostr(hiBit - loBit) +
-                     ", " + itostr(loBit) + ")";
-        Case += "      Value.insertBits(" + extractStr + ", " +
-                itostr(loInstBit) + ", " + itostr(hiBit - loBit) + ");\n";
+        ExtractStr = "op.extractBitsAsZExtValue(" + itostr(HiBit - LoBit) +
+                     ", " + itostr(LoBit) + ")";
+        Case += "      Value.insertBits(" + ExtractStr + ", " +
+                itostr(LoInstBit) + ", " + itostr(HiBit - LoBit) + ");\n";
       }
     } else {
-      uint64_t opMask = ~(uint64_t)0 >> (64 - N);
-      opShift = beginVarBit - N + 1;
-      opMask <<= opShift;
-      maskStr = "UINT64_C(" + utostr(opMask) + ")";
-      opShift = beginInstBit - beginVarBit;
-
-      if (numOperandLits == 1) {
-        Case += "      op &= " + maskStr + ";\n";
-        if (opShift > 0) {
-          Case += "      op <<= " + itostr(opShift) + ";\n";
-        } else if (opShift < 0) {
-          Case += "      op >>= " + itostr(-opShift) + ";\n";
+      uint64_t OpMask = ~(uint64_t)0 >> (64 - N);
+      OpShift = BeginVarBit - N + 1;
+      OpMask <<= OpShift;
+      MaskStr = "UINT64_C(" + utostr(OpMask) + ")";
+      OpShift = BeginInstBit - BeginVarBit;
+
+      if (NumOperandLits == 1) {
+        Case += "      op &= " + MaskStr + ";\n";
+        if (OpShift > 0) {
+          Case += "      op <<= " + itostr(OpShift) + ";\n";
+        } else if (OpShift < 0) {
+          Case += "      op >>= " + itostr(-OpShift) + ";\n";
         }
         Case += "      Value |= op;\n";
       } else {
-        if (opShift > 0) {
-          Case += "      Value |= (op & " + maskStr + ") << " +
-                  itostr(opShift) + ";\n";
-        } else if (opShift < 0) {
-          Case += "      Value |= (op & " + maskStr + ") >> " +
-                  itostr(-opShift) + ";\n";
+        if (OpShift > 0) {
+          Case += "      Value |= (op & " + MaskStr + ") << " +
+                  itostr(OpShift) + ";\n";
+        } else if (OpShift < 0) {
+          Case += "      Value |= (op & " + MaskStr + ") >> " +
+                  itostr(-OpShift) + ";\n";
         } else {
-          Case += "      Value |= (op & " + maskStr + ");\n";
+          Case += "      Value |= (op & " + MaskStr + ");\n";
         }
       }
     }
@@ -285,7 +285,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
                                     const CodeGenTarget &Target) {
   std::string Case, BitOffsetCase;
 
-  auto append = [&](const std::string &S) {
+  auto Append = [&](const std::string &S) {
     Case += S;
     BitOffsetCase += S;
   };
@@ -298,7 +298,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
       // Invoke the interface to obtain the HwMode ID controlling the
       // EncodingInfo for the current subtarget. This interface will
       // mask off irrelevant HwMode IDs.
-      append("      unsigned HwMode = "
+      Append("      unsigned HwMode = "
              "STI.getHwMode(MCSubtargetInfo::HwMode_EncodingInfo);\n");
       Case += "      switch (HwMode) {\n";
       Case += "      default: llvm_unreachable(\"Unknown hardware mode!\"); "
@@ -328,16 +328,16 @@ CodeEmitterGen::getInstructionCases(const Record *R,
         Case += "      Value = InstBitsByHw[opcode];\n";
       }
 
-      append("      switch (HwMode) {\n");
-      append("      default: llvm_unreachable(\"Unhandled HwMode\");\n");
+      Append("      switch (HwMode) {\n");
+      Append("      default: llvm_unreachable(\"Unhandled HwMode\");\n");
       for (auto &[ModeId, Encoding] : EBM) {
-        append("      case " + itostr(ModeId) + ": {\n");
+        Append("      case " + itostr(...
[truncated]

``````````

</details>


https://github.com/llvm/llvm-project/pull/113318


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