[llvm] [AArch64]Add convert and multiply-add SIMD&FP assembly/disassembly in… (PR #113296)

[Jonathan Thackray via llvm-commits]

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@@ -5190,6 +5218,32 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
   }
 }
 
+multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator node = null_frag> {
+  // 32-bit to half-precision
+  def HSr: BaseIntegerToFPUnscaled<rmode, opcode, FPR32, FPR16, f16, asm, node> {
+    let Inst{31} = 0; // 32-bit GPR flag
+    let Inst{23-22} = 0b11; // 16-bit FPR flag
+  }
+
+  // 32-bit to double-precision
+  def DSr: BaseIntegerToFPUnscaled<rmode, opcode, FPR32, FPR64, f64, asm, node> {
+    let Inst{31} = 0; // 32-bit GPR flag
+    let Inst{23-22} = 0b01; // 16-bit FPR flag
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jthackray wrote:

The comment here ("16-bit FPR flag") and on line 5225 are the same, but the bit patterns different. Typo?

https://github.com/llvm/llvm-project/pull/113296