[llvm] [MachinePipeliner] Add an abstract layer to manipulate Data Dependenc… (PR #109918)

[Ryotaro Kasuga via llvm-commits]

kasuga-fj wrote:

> I'm not sure what the godbolt link you've supplied is supposed to show, as there isn't a loop, so you can't say anything about whether loop-carried dependences are handled correctly. The proper output and anti-dependencies for the MIR are present in the data graph. One might argue that an anti-dependence between SU(1) and SU(4) is missing, but the anti-dependence from 1->2 combined with the output dependence from 2->4 make it unnecessary, and I think the DDG builder might notice that.

Sorry, something was wrong with the my previous godbolt link. The following is the correct one.

https://godbolt.org/z/3v5rnPG3o

I think that the loop-carried dependence SU(5) -> SU(2) is not handled correctly in the current implementation\. If we're just talking about this case, it doesn't matter because instructions that read/write `$nzcv` (which I think is equivalent to `$cpsr` in ARM) are ultimately scheduled to stage 0\. However, the problem can occur if similar dependencies are created by any other different physical registers\. As fixed in https://github.com/llvm/llvm-project/commit/dcb77643e3440e948010ed8ecb4c2f8fe4fadb93, dependencies created by the status register are handled correctly, but those created by other physical registers seem not to be\. I'm not sure if such dependencies exist, but I think FFR register of Arm SVE could create such one\. This is what I meant in the previous comment "should be fixed to treat other loop-carried dependencies correctly in the future".

https://github.com/llvm/llvm-project/pull/109918