[llvm] [LLVM][AArch64] Add assembly/disassembly of SVE BFSCALE instruction (PR #113168)

[via llvm-commits]

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@@ -2174,6 +2174,10 @@ multiclass sve_fp_2op_p_zds_bfloat<bits<4> opc, string asm, string Ps,
   def : SVE_3_Op_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME)>;
 }
 
+class  sve_fp_2op_p_zds_bfscale<bits<4> opc, string asm,  DestructiveInstTypeEnum flags> : sve_fp_2op_p_zds<0b00, opc, asm, ZPR16>{
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CarolineConcatto wrote:

nit: formating

class  sve_fp_2op_p_zds_bfscale<bits<4> opc, string asm,  DestructiveInstTypeEnum flags> 
  : sve_fp_2op_p_zds<0b00, opc, asm, ZPR16>{
  let DestructiveInstType = flags;
  }


https://github.com/llvm/llvm-project/pull/113168