[llvm] [LLVM][AArch64] Add assembly/disassembly of SVE BFSCALE instruction (PR #113168)

[via llvm-commits]

================
@@ -19,3 +19,8 @@ rax1 z0.d, z0.d, z0.d
 .cpu generic+sve2-bitperm
 bgrp z21.s, z10.s, z21.s
 // CHECK: bgrp z21.s, z10.s, z21.s
+
+.cpu generic+sve-bfscale
+bfscale z0.h, p0/m, z0.h, z0.h
+// CHECK-d: error: instruction requires: sve-bfscale
----------------
SpencerAbson wrote:

This line above may be a typo?

https://github.com/llvm/llvm-project/pull/113168