[llvm] f2302ed - [RISCV][GISEL] Fix operand on RISCV::G_VMV_V_V_VL

[Michael Maitland via llvm-commits]

Author: Michael Maitland
Date: 2024-10-21T06:58:12-07:00
New Revision: f2302ed3d0f84ca867a3e664ed65bc89e52ee670

URL: https://github.com/llvm/llvm-project/commit/f2302ed3d0f84ca867a3e664ed65bc89e52ee670
DIFF: https://github.com/llvm/llvm-project/commit/f2302ed3d0f84ca867a3e664ed65bc89e52ee670.diff

LOG: [RISCV][GISEL] Fix operand on RISCV::G_VMV_V_V_VL

6bac41496eb24c80aa659008d08220355a617c49 added this opcode with the wrong
number of operands. It didn't fail on check-llvm for me or on pre-commit CI,
but once committed we got buildbot failures. This patch fixes the definition
of the instruction and fixes the failing test.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrGISel.td
    llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrGISel.td b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
index 80f1901513b6ef..763aead84dd8f4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
@@ -70,7 +70,7 @@ def : GINodeEquiv<G_VSLIDEDOWN_VL, riscv_slidedown_vl>;
 // Pseudo equivalent to a RISCVISD::VMV_V_V_VL
 def G_VMV_V_V_VL : RISCVGenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$vec, type2:$vl);
+  let InOperandList = (ins type0:$passthru, type0:$vec, type1:$vl);
   let hasSideEffects = false;
 }
 def : GINodeEquiv<G_VMV_V_V_VL, riscv_vmv_v_v_vl>;

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
index 68c5ae12047493..81a3a0c7ddd03a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
@@ -538,7 +538,7 @@ body:             |
     ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
     ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
     ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C1]](s64)
-    ; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]](<vscale x 4 x s16>), [[LSHR]](s64)
+    ; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]], [[LSHR]](s64)
     ; RV32-NEXT: [[INSERT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[COPY]], [[VMV_V_V_VL]](<vscale x 4 x s16>), 4
     ; RV32-NEXT: $v8 = COPY [[INSERT_SUBVECTOR1]](<vscale x 8 x s16>)
     ; RV32-NEXT: PseudoRET implicit $v8
@@ -556,7 +556,7 @@ body:             |
     ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
     ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
     ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C1]](s32)
-    ; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]](<vscale x 4 x s16>), [[LSHR]](s32)
+    ; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]], [[LSHR]](s32)
     ; RV64-NEXT: [[INSERT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[COPY]], [[VMV_V_V_VL]](<vscale x 4 x s16>), 4
     ; RV64-NEXT: $v8 = COPY [[INSERT_SUBVECTOR1]](<vscale x 8 x s16>)
     ; RV64-NEXT: PseudoRET implicit $v8