[llvm] [AArch64] Add assembly/disaasembly of atomic ld/st (PR #112892)

[via llvm-commits]

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@@ -12626,3 +12626,64 @@ def : TokenAlias<".H", ".h">;
 def : TokenAlias<".S", ".s">;
 def : TokenAlias<".D", ".d">;
 def : TokenAlias<".Q", ".q">;
+
+//----------------------------------------------------------------------------
+// 2024 Armv9.6 Extensions
+//----------------------------------------------------------------------------
+
+let mayLoad = 1, mayStore = 1 in
+class BaseAtomicFPLoad<RegisterClass regtype, bits<2> sz, bits<2> AR,
+                     bits<3> op0, string asm>
+: I<(outs regtype:$Rt),
+    (ins regtype:$Rs, GPR64sp:$Rn),
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Lukacma wrote:

Why do you think Rs is the destination register ? My pseudocode in [spec](https://developer.arm.com/documentation/ddi0602/2024-09/SIMD-FP-Instructions/LDBFMINNM--LDBFMINNMA--LDBFMINNMAL--LDBFMINNML--BFloat16-floating-point-atomic-minimum-number-in-memory-?lang=en) suggests it should be Rt, or am I missing smth here ?

https://github.com/llvm/llvm-project/pull/112892