[llvm] [IR] Add `llvm.sincos` intrinsic (PR #109825)

[Benjamin Maxwell via llvm-commits]

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@@ -4749,6 +4755,14 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::VP_FSHR:
     Res = WidenVecRes_Ternary(N);
     break;
+  case ISD::FSINCOS: {
+    if (!unrollExpandedOp())
+      Res = WidenVecRes_FSINCOS(N);
+    for (unsigned ResNum = 0; ResNum < N->getNumValues(); ResNum++)
+      SetWidenedVector(SDValue(N, ResNum), Res.getValue(ResNum));
+    Res = SDValue();
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MacDue wrote:

Done this now, and enabled widening for `FREXPR` (with two AArch64 tests).

https://github.com/llvm/llvm-project/pull/109825