[llvm] [AMDGPU] Implement hasAndNot for scalar bitwise AND-NOT operations. (PR #112647)

[Vikash Gupta via llvm-commits]

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@@ -16890,3 +16889,13 @@ SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
   AI->eraseFromParent();
   return LI;
 }
+
+bool SITargetLowering::hasAndNot(SDValue Op) const {
+  // Return false if the operation is divergent, as AND-NOT is a scalar-only
+  // instruction.
+  if (Op->isDivergent() || !Op->isMachineOpcode())
+    return false;
+
+  EVT VT = Op.getValueType();
+  return VT == MVT::i32 || VT == MVT::i64;
+}
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vg0204 wrote:

@arsenm, just checking for i32 & i64 is sufficient on hardware behalf to say it has AndNot support?

https://github.com/llvm/llvm-project/pull/112647