[llvm] [PPC] Add custom lowering for uaddo (PR #110137)

[Maryam Moghadas via llvm-commits]

================
@@ -11967,11 +11969,45 @@ SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
   llvm_unreachable("ERROR:Should return for all cases within swtich.");
 }
 
+SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const {
+  // Default to target independent lowering if there is a logical user of the
+  // carry-bit.
+  for (SDNode *U : Op->uses()) {
+    if (U->getOpcode() == ISD::SELECT || ISD::isBitwiseLogicOp(U->getOpcode()))
+      return SDValue();
----------------
maryammo wrote:

This prevents the following case to get custom lowered, however with custom lowering the final assembly looks better. There are 2 uaddo's which are used by logical or in the dag. 

```
unsigned long long add(unsigned long long a, unsigned long long b, unsigned long long c, unsigned long long *ovf)
{
     return __builtin_addcll(a,b,c,ovf);
}
```

$ clang -O3 -mcpu=power8 -m64 -S 
Assembly with default target independent lowering:
```
.add:
# %bb.0:                                # %entry
        add 4, 3, 4
        subc    3, 4, 3
        subfe 3, 4, 4
        neg 7, 3
        add 3, 4, 5
        subc    4, 3, 4
        subfe 4, 3, 3
        neg 4, 4
        or 4, 7, 4
        std 4, 0(6)
        blr 
```
Assembly with custom lowering:
```
.add:
# %bb.0:                                # %entry
        li 7, 0
        addc 3, 3, 4
        addze 4, 7
        addc 3, 3, 5
        addze 5, 7
        or 4, 4, 5
        std 4, 0(6)
        blr 
```


https://github.com/llvm/llvm-project/pull/110137