[llvm] [RISCV] Account for factor in interleave memory op costs (PR #111511)

[Craig Topper via llvm-commits]

topperc wrote:

For x280, I think factor 2 is handled pretty much like a unit stride load. It reads/writes two register at once.

Other factors are handled one segment at a time. If the segment is more than DLEN bits then each segment will require multiple cycles. So the cost is something like VL*ceil(DLEN/(SEW*factor)). There's probably also some register file write port cost too, but I don't know exactly.

https://github.com/llvm/llvm-project/pull/111511