[llvm] [LLVM][AArch64] Add register classes for Armv9.6 assembly (PR #111717)

[Momchil Velikov via llvm-commits]

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@@ -1124,23 +1126,28 @@ let EncoderMethod = "EncodeRegAsMultipleOf<2>",
 //******************************************************************************
 
 // SVE vector register classes
-class ZPRClass<int lastreg> : RegisterClass<"AArch64",
+class ZPRClass<int firstreg, int lastreg, int step = 1> : RegisterClass<"AArch64",
                                             [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
                                              nxv2f16, nxv4f16, nxv8f16,
                                              nxv2bf16, nxv4bf16, nxv8bf16,
                                              nxv2f32, nxv4f32,
                                              nxv2f64],
-                                            128, (sequence "Z%u", 0, lastreg)> {
+                                            128, (sequence "Z%u", firstreg, lastreg, step)> {
   let Size = 128;
 }
 
-def ZPR    : ZPRClass<31> {
+def ZPRMul2    : ZPRClass<0,  30, 2>;
+def ZPRMul4    : ZPRClass<0,  28, 4>;
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momchil-velikov wrote:

I wonder how would that work. In `isTypedVectorListMultiple` the `RegClass` template parameter denotes the register class of the elements of the vector list. If `ZPRMul2`/`ZPRMul4`, which are sets of single registers, can be used interchangeably with `ZPR2Mul2`/`ZPR4Mul4`, which are sets of register pairs/quadruples, something somewhere is very broken.

https://github.com/llvm/llvm-project/pull/111717