[llvm] [llvm][ARM] Add Addend Checks for MOVT and MOVW instructions. (PR #111970)

[Jack Styles via llvm-commits]

================
@@ -125,6 +125,11 @@ Changes to the ARM Backend
   the required alignment space with a sequence of `0x0` bytes (the requested
   fill value) rather than NOPs.
 
+* When using the `MOVT` or `MOVW` instructions, the Assembler will now check to
+  ensure that any addend that is used is within a 16bit Signed value range. If the
----------------
Stylie777 wrote:

Updated

https://github.com/llvm/llvm-project/pull/111970