[llvm] 870d37d - [AMDGPU] Rewrite RegSeqNames using !foreach. NFC. (#111994)

[via llvm-commits]

Author: Jay Foad
Date: 2024-10-11T14:08:07+01:00
New Revision: 870d37dd1257d211f96797bf041280b2260ed260

URL: https://github.com/llvm/llvm-project/commit/870d37dd1257d211f96797bf041280b2260ed260
DIFF: https://github.com/llvm/llvm-project/commit/870d37dd1257d211f96797bf041280b2260ed260.diff

LOG: [AMDGPU] Rewrite RegSeqNames using !foreach. NFC. (#111994)

This reduces the total number of TableGen records produced by AMDGPU.td
by about 6%.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index ef9adde13348fe..3556f6a95b521e 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -88,15 +88,10 @@ class getSubRegs<int size> {
 
 // Generates list of sequential register tuple names.
 // E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ]
-class RegSeqNames<int last_reg, int stride, int size, string prefix,
-                  int start = 0> {
-  int next = !add(start, stride);
-  int end_reg = !add(start, size, -1);
-  list<string> ret =
-    !if(!le(end_reg, last_reg),
-        !listconcat([prefix # "[" # start # ":" # end_reg # "]"],
-                    RegSeqNames<last_reg, stride, size, prefix, next>.ret),
-                    []);
+class RegSeqNames<int last_reg, int stride, int size, string prefix> {
+  defvar numtuples = !div(!sub(!add(last_reg, stride, 1), size), stride);
+  defvar range = !range(0, !mul(numtuples, stride), stride);
+  list<string> ret = !foreach(n, range, prefix # "[" # n # ":" # !add(n, size, -1) # "]");
 }
 
 // Generates list of dags for register tuples.