[llvm] [RISCV] Add DAG combine to turn (sub (shl X, 8-Y), (shr X, Y)) into orc.b (PR #111828)

Daniel Mokeev via llvm-commits llvm-commits at lists.llvm.org
Fri Oct 11 05:58:57 PDT 2024

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damokeev wrote:

Thanks! Sorry again for the git issues.

https://github.com/llvm/llvm-project/pull/111828

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Next message: [llvm] [LoongArch] Pass 'half' in the lower 16 bits of an f32 value with F/D ABI (PR #109368)
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