[llvm] Add Addend Checks for MOVT and MOVW instructions. (PR #111970)
Jack Styles via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 11 02:29:48 PDT 2024
https://github.com/Stylie777 created https://github.com/llvm/llvm-project/pull/111970
Previously, any value could be used for the MOVT and MOVW instructions, however the ARM ABI dictates that the addend should be a signed 16 bit value. To ensure this is followed, the Assembler will now check that when using these instructions, the addend is a 16bit signed value, and throw an error if this is not the case.
>From d75fd29c6f1473d501cbb31615f9feeafaf7605f Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Wed, 10 Jul 2024 11:28:48 +0100
Subject: [PATCH 1/4] [AArch64] Update AUTIxSPPC and RETAxSPPC instructions for
register variant.
As of the 2024.06 Arm Architecture release, the register variants of the
AUTIxSPPC and RETAxSPPC instructions have been updated to be explicitly
different to the immediate variant. The instructions now follow the format
AUTIxSPPCR and RETAxSPPCR for the register variants, with the immediate
variants keeping their current form.
The Specs can be found at the following locations
AUTIASPPCR: https://developer.arm.com/documentation/ddi0602/2024-06/Base-Instructions/AUTIASPPCR--Authenticate-return-address-using-key-A--using-a-register-?lang=en
AUTIBSPPCR: https://developer.arm.com/documentation/ddi0602/2024-06/Base-Instructions/AUTIBSPPCR--Authenticate-return-address-using-key-B--using-a-register-?lang=en
RETAASPPCR and RETABSPPCR: https://developer.arm.com/documentation/ddi0602/2024-06/Base-Instructions/RETAASPPCR--RETABSPPCR--Return-from-subroutine--with-enhanced-pointer-authentication-return-using-a-register-?lang=en
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 ++---
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 36 +++++++++----------
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 12 +++----
3 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 78c8bf1e323aba..bafcafb7d8d4ac 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1845,8 +1845,8 @@ let Predicates = [HasPAuthLR] in {
def AUTIASPPCi : SignAuthPCRel<0b00, "autiasppc">;
def AUTIBSPPCi : SignAuthPCRel<0b01, "autibsppc">;
// opcode2, opcode, asm
- def AUTIASPPCr : SignAuthOneReg<0b00001, 0b100100, "autiasppc">;
- def AUTIBSPPCr : SignAuthOneReg<0b00001, 0b100101, "autibsppc">;
+ def AUTIASPPCr : SignAuthOneReg<0b00001, 0b100100, "autiasppcr">;
+ def AUTIBSPPCr : SignAuthOneReg<0b00001, 0b100101, "autibsppcr">;
// opcode2, opcode, asm
def PACIA171615 : SignAuthFixedRegs<0b00001, 0b100010, "pacia171615">;
def PACIB171615 : SignAuthFixedRegs<0b00001, 0b100011, "pacib171615">;
@@ -1859,8 +1859,8 @@ let Predicates = [HasPAuthLR] in {
def RETAASPPCi : SignAuthReturnPCRel<0b000, 0b11111, "retaasppc">;
def RETABSPPCi : SignAuthReturnPCRel<0b001, 0b11111, "retabsppc">;
// op3, asm
- def RETAASPPCr : SignAuthReturnReg<0b000010, "retaasppc">;
- def RETABSPPCr : SignAuthReturnReg<0b000011, "retabsppc">;
+ def RETAASPPCr : SignAuthReturnReg<0b000010, "retaasppcr">;
+ def RETABSPPCr : SignAuthReturnReg<0b000011, "retabsppcr">;
}
def : InstAlias<"pacm", (PACM), 1>;
}
diff --git a/llvm/test/MC/AArch64/armv9.5a-pauthlr.s b/llvm/test/MC/AArch64/armv9.5a-pauthlr.s
index 2bc84c13f70ff0..2655798852892c 100644
--- a/llvm/test/MC/AArch64/armv9.5a-pauthlr.s
+++ b/llvm/test/MC/AArch64/armv9.5a-pauthlr.s
@@ -70,30 +70,30 @@ label1:
// CHECK-ERROR: instruction requires: pauth-lr
// CHECK-UNKNOWN: f3bfffff <unknown>
- autiasppc x0
-// CHECK-INST: autiasppc x0
-// CHECK-DISASS: autiasppc x0
+ autiasppcr x0
+// CHECK-INST: autiasppcr x0
+// CHECK-DISASS: autiasppcr x0
// CHECK-ENCODING: [0x1e,0x90,0xc1,0xda]
// CHECK-ERROR: instruction requires: pauth-lr
// CHECK-UNKNOWN: dac1901e <unknown>
- autibsppc x1
-// CHECK-INST: autibsppc x1
-// CHECK-DISASS: autibsppc x1
+ autibsppcr x1
+// CHECK-INST: autibsppcr x1
+// CHECK-DISASS: autibsppcr x1
// CHECK-ENCODING: [0x3e,0x94,0xc1,0xda]
// CHECK-ERROR: instruction requires: pauth-lr
// CHECK-UNKNOWN: dac1943e <unknown>
- autiasppc xzr
-// CHECK-INST: autiasppc xzr
-// CHECK-DISASS: autiasppc xzr
+ autiasppcr xzr
+// CHECK-INST: autiasppcr xzr
+// CHECK-DISASS: autiasppcr xzr
// CHECK-ENCODING: [0xfe,0x93,0xc1,0xda]
// CHECK-ERROR: instruction requires: pauth-lr
// CHECK-UNKNOWN: dac193fe <unknown>
- autibsppc xzr
-// CHECK-INST: autibsppc xzr
-// CHECK-DISASS: autibsppc xzr
+ autibsppcr xzr
+// CHECK-INST: autibsppcr xzr
+// CHECK-DISASS: autibsppcr xzr
// CHECK-ENCODING: [0xfe,0x97,0xc1,0xda]
// CHECK-ERROR: instruction requires: pauth-lr
// CHECK-UNKNOWN: dac197fe <unknown>
@@ -156,16 +156,16 @@ label1:
// CHECK-ERROR: instruction requires: pauth-lr
// CHECK-UNKNOWN: 551fffff <unknown>
- retaasppc x2
-// CHECK-INST: retaasppc x2
-// CHECK-DISASS: retaasppc x2
+ retaasppcr x2
+// CHECK-INST: retaasppcr x2
+// CHECK-DISASS: retaasppcr x2
// CHECK-ENCODING: [0xe2,0x0b,0x5f,0xd6]
// CHECK-ERROR: instruction requires: pauth-lr
// CHECK-UNKNOWN: d65f0be2 <unknown>
- retabsppc x3
-// CHECK-INST: retabsppc x3
-// CHECK-DISASS: retabsppc x3
+ retabsppcr x3
+// CHECK-INST: retabsppcr x3
+// CHECK-DISASS: retabsppcr x3
// CHECK-ENCODING: [0xe3,0x0f,0x5f,0xd6]
// CHECK-ERROR: instruction requires: pauth-lr
// CHECK-UNKNOWN: d65f0fe3 <unknown>
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
index 53d78023bc4b48..d5e809f19928d1 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
@@ -34,19 +34,19 @@
# NO-PAUTHLR: invalid instruction encoding
[0x1e,0x90,0xc1,0xda]
-# CHECK: autiasppc x0
+# CHECK: autiasppcr x0
# NO-PAUTHLR: invalid instruction encoding
[0x3e,0x94,0xc1,0xda]
-# CHECK: autibsppc x1
+# CHECK: autibsppcr x1
# NO-PAUTHLR: invalid instruction encoding
[0xfe,0x93,0xc1,0xda]
-# CHECK: autiasppc xzr
+# CHECK: autiasppcr xzr
# NO-PAUTHLR: invalid instruction encoding
[0xfe,0x97,0xc1,0xda]
-# CHECK: autibsppc xzr
+# CHECK: autibsppcr xzr
# NO-PAUTHLR: invalid instruction encoding
[0xfe,0x8b,0xc1,0xda]
@@ -82,11 +82,11 @@
# NO-PAUTHLR: invalid instruction encoding
[0xe2,0x0b,0x5f,0xd6]
-# CHECK: retaasppc x2
+# CHECK: retaasppcr x2
# NO-PAUTHLR: invalid instruction encoding
[0xe3,0x0f,0x5f,0xd6]
-# CHECK: retabsppc x3
+# CHECK: retabsppcr x3
# NO-PAUTHLR: invalid instruction encoding
[0xff,0x24,0x03,0xd5]
>From cff9983a0e319332453ebea324b3cd92d64330a3 Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Fri, 4 Oct 2024 15:19:01 +0100
Subject: [PATCH 2/4] [ARM][MC] Add Range Checks for MOVT and MOVW Instructions
As per the ARM ABI, the MOVT and MOVW instructions should have
addends that fall within a 16bit signed range. LLVM does not check
this so it is possible to use addends that are beyond the accepted
range. These addends are silently truncated.
A new check is added to ensure the addend falls within the expected
range, rejecting an addend that falls outside with an error.
Information relating to the ABI requirements can be found here:
https://github.com/ARM-software/abi-aa/blob/main/aaelf32/aaelf32.rst#addends-and-pc-bias-compensation
---
.../Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 9 +++++++++
llvm/test/MC/ARM/arm-movt-movw-range-fail.s | 13 +++++++++++++
llvm/test/MC/ARM/arm-movt-movw-range-pass.s | 13 +++++++++++++
llvm/test/MC/ARM/macho-movwt.s | 16 ++++++++--------
4 files changed, 43 insertions(+), 8 deletions(-)
create mode 100644 llvm/test/MC/ARM/arm-movt-movw-range-fail.s
create mode 100644 llvm/test/MC/ARM/arm-movt-movw-range-pass.s
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 1223210a76f6e3..184bc28a6653b2 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -34,6 +34,7 @@
#include "llvm/Support/EndianStream.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -472,11 +473,19 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
case FK_SecRel_4:
return Value;
case ARM::fixup_arm_movt_hi16:
+ if(!(minIntN(16) <= static_cast<int64_t>(Value) && static_cast<int64_t>(Value) <= maxIntN(16))) {
+ Ctx.reportError(Fixup.getLoc(), "Relocation Not In Range");
+ return 0;
+ }
assert(STI != nullptr);
if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
Value >>= 16;
[[fallthrough]];
case ARM::fixup_arm_movw_lo16: {
+ if(!(minIntN(16) <= static_cast<int64_t>(Value) && static_cast<int64_t>(Value) <= maxIntN(16))) {
+ Ctx.reportError(Fixup.getLoc(), "Relocation Not In Range");
+ return 0;
+ }
unsigned Hi4 = (Value & 0xF000) >> 12;
unsigned Lo12 = Value & 0x0FFF;
// inst{19-16} = Hi4;
diff --git a/llvm/test/MC/ARM/arm-movt-movw-range-fail.s b/llvm/test/MC/ARM/arm-movt-movw-range-fail.s
new file mode 100644
index 00000000000000..2961b9bfcb64d2
--- /dev/null
+++ b/llvm/test/MC/ARM/arm-movt-movw-range-fail.s
@@ -0,0 +1,13 @@
+ at RUN: not llvm-mc -triple armv7-eabi -filetype obj -o - %s 2>&1 | FileCheck %s
+
+ .global v
+ .text
+ movw r1, #:lower16:v + -65536
+ movt r1, #:upper16:v + 65536
+
+ at CHECK: error: Relocation Not In Range
+ at CHECK: movw r1, #:lower16:v + -65536
+ at CHECK: ^
+ at CHECK: error: Relocation Not In Range
+ at CHECK: movt r1, #:upper16:v + 65536
+ at CHECK: ^
diff --git a/llvm/test/MC/ARM/arm-movt-movw-range-pass.s b/llvm/test/MC/ARM/arm-movt-movw-range-pass.s
new file mode 100644
index 00000000000000..41f19565a46c4a
--- /dev/null
+++ b/llvm/test/MC/ARM/arm-movt-movw-range-pass.s
@@ -0,0 +1,13 @@
+ at RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s 2>&1 | FileCheck %s
+
+ .global v
+ .text
+ movw r1, #:lower16:v + -20000
+ movt r1, #:upper16:v + 20000
+
+ at CHECK-NOT: error: Relocation Not In Range
+ at CHECK-NOT: movw r1, #:lower16:v + -20000
+ at CHECK-NOT: ^
+ at CHECK-NOT: error: Relocation Not In Range
+ at CHECK-NOT: movt r1, #:upper16:v + 20000
+ at CHECK-NOT: ^
diff --git a/llvm/test/MC/ARM/macho-movwt.s b/llvm/test/MC/ARM/macho-movwt.s
index 6f067cd86dc15d..b2c0587ca7fe59 100644
--- a/llvm/test/MC/ARM/macho-movwt.s
+++ b/llvm/test/MC/ARM/macho-movwt.s
@@ -8,8 +8,8 @@
movw r0, :lower16:_x+4
movt r0, :upper16:_x+4
- movw r0, :lower16:_x+0x10000
- movt r0, :upper16:_x+0x10000
+ movw r0, :lower16:_x+0x1000
+ movt r0, :upper16:_x+0x1000
.arm
movw r0, :lower16:_x
@@ -18,8 +18,8 @@
movw r0, :lower16:_x+4
movt r0, :upper16:_x+4
- movw r0, :lower16:_x+0x10000
- movt r0, :upper16:_x+0x10000
+ movw r0, :lower16:_x+0x1000
+ movt r0, :upper16:_x+0x1000
@ Enter the bizarre world of MachO relocations. First, they're in reverse order
@ to the actual instructions
@@ -30,10 +30,10 @@
@ Third column identifies ARM/Thumb & HI/LO.
@ CHECK: 0x2C 0 1 1 ARM_RELOC_HALF 0 _x
-@ CHECK: 0x0 0 1 0 ARM_RELOC_PAIR 0 -
+@ CHECK: 0x1000 0 1 0 ARM_RELOC_PAIR 0 -
@ CHECK: 0x28 0 0 1 ARM_RELOC_HALF 0 _x
-@ CHECK: 0x1 0 0 0 ARM_RELOC_PAIR 0 -
+@ CHECK: 0x0 0 0 0 ARM_RELOC_PAIR 0 -
@ CHECK: 0x24 0 1 1 ARM_RELOC_HALF 0 _x
@ CHECK: 0x4 0 1 0 ARM_RELOC_PAIR 0 -
@@ -48,10 +48,10 @@
@ CHECK: 0x0 0 0 0 ARM_RELOC_PAIR 0 -
@ CHECK: 0x14 0 3 1 ARM_RELOC_HALF 0 _x
-@ CHECK: 0x0 0 3 0 ARM_RELOC_PAIR 0 -
+@ CHECK: 0x1000 0 3 0 ARM_RELOC_PAIR 0 -
@ CHECK: 0x10 0 2 1 ARM_RELOC_HALF 0 _x
-@ CHECK: 0x1 0 2 0 ARM_RELOC_PAIR 0 -
+@ CHECK: 0x0 0 2 0 ARM_RELOC_PAIR 0 -
@ CHECK: 0xC 0 3 1 ARM_RELOC_HALF 0 _x
@ CHECK: 0x4 0 3 0 ARM_RELOC_PAIR 0 -
>From aad5f1a2f4d756f7b21efcbe4c9ad35b677126ae Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Fri, 11 Oct 2024 09:34:24 +0100
Subject: [PATCH 3/4] [ARM] Check for addend before the Value is adjusted
As part of the checks, in some cases the Value is changed according
to if the Thumb bit is needed. This changes the value and can cause
the calcuation to check the range to falsely fail.
Moving the check before the Value is changed to ensure this cannot
occur.
Previously, tests existed that exploited the truncation of the
addend into a 16bit signed value, so these tests have been updated
to reflect the fact this is no longer allowed. It still tests the
instruction, but the expected outcome has been updated with new
values.
---
.../Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 18 ++++++++++--------
llvm/test/MC/ARM/Windows/mov32t-range.s | 6 +++---
llvm/test/MC/MachO/ARM/thumb2-movw-fixup.s | 10 +++++-----
3 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 184bc28a6653b2..4d643d001d7541 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -447,6 +447,16 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
const MCSubtargetInfo* STI) const {
unsigned Kind = Fixup.getKind();
+ // For MOVW/MOVT Instructions, the Fixup Value needs to be 16 bit aligned.
+ // If this is not the case, we should reject compilation.
+ if((Kind == ARM::fixup_arm_movw_lo16 || Kind == ARM::fixup_arm_movt_hi16 ||
+ Kind == ARM::fixup_t2_movw_lo16 || Kind == ARM::fixup_t2_movt_hi16) &&
+ (!(minIntN(16) <= static_cast<int64_t>(Value) &&
+ static_cast<int64_t>(Value) <= maxIntN(16)))) {
+ Ctx.reportError(Fixup.getLoc(), "Relocation Not In Range");
+ return 0;
+ }
+
// MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
// and .word relocations they put the Thumb bit into the addend if possible.
// Other relocation types don't want this bit though (branches couldn't encode
@@ -473,19 +483,11 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
case FK_SecRel_4:
return Value;
case ARM::fixup_arm_movt_hi16:
- if(!(minIntN(16) <= static_cast<int64_t>(Value) && static_cast<int64_t>(Value) <= maxIntN(16))) {
- Ctx.reportError(Fixup.getLoc(), "Relocation Not In Range");
- return 0;
- }
assert(STI != nullptr);
if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
Value >>= 16;
[[fallthrough]];
case ARM::fixup_arm_movw_lo16: {
- if(!(minIntN(16) <= static_cast<int64_t>(Value) && static_cast<int64_t>(Value) <= maxIntN(16))) {
- Ctx.reportError(Fixup.getLoc(), "Relocation Not In Range");
- return 0;
- }
unsigned Hi4 = (Value & 0xF000) >> 12;
unsigned Lo12 = Value & 0x0FFF;
// inst{19-16} = Hi4;
diff --git a/llvm/test/MC/ARM/Windows/mov32t-range.s b/llvm/test/MC/ARM/Windows/mov32t-range.s
index 7e16105cddc6f3..386893a078de40 100644
--- a/llvm/test/MC/ARM/Windows/mov32t-range.s
+++ b/llvm/test/MC/ARM/Windows/mov32t-range.s
@@ -21,7 +21,7 @@ truncation:
.section .rdata,"rd"
.Lbuffer:
- .zero 65536
+ .zero 32767
.Lerange:
.asciz "-erange"
@@ -32,6 +32,6 @@ truncation:
@ CHECK-RELOCATIONS: }
@ CHECK-RELOCATIONS: ]
-@ CHECK-ENCODING: 0: f240 0000
-@ CHECK-ENCODING-NEXT: 4: f2c0 0001
+@ CHECK-ENCODING: 0: f647 70ff
+@ CHECK-ENCODING-NEXT: 4: f2c0 0000
diff --git a/llvm/test/MC/MachO/ARM/thumb2-movw-fixup.s b/llvm/test/MC/MachO/ARM/thumb2-movw-fixup.s
index 18182d1affb063..0d6f38325b1d3c 100644
--- a/llvm/test/MC/MachO/ARM/thumb2-movw-fixup.s
+++ b/llvm/test/MC/MachO/ARM/thumb2-movw-fixup.s
@@ -11,7 +11,7 @@
movt r2, :upper16:L1
movw r12, :lower16:L2
movt r12, :upper16:L2
- .space 70000
+ .space 16382
.data
L1: .long 0
@@ -30,7 +30,7 @@ L2: .long 0
@ CHECK: Section: __data (2)
@ CHECK: }
@ CHECK: Relocation {
-@ CHECK: Offset: 0x1184
+@ CHECK: Offset: 0x4012
@ CHECK: PCRel: 0
@ CHECK: Length: 3
@ CHECK: Type: ARM_RELOC_PAIR (1)
@@ -44,7 +44,7 @@ L2: .long 0
@ CHECK: Section: __data (2)
@ CHECK: }
@ CHECK: Relocation {
-@ CHECK: Offset: 0x1
+@ CHECK: Offset: 0x0
@ CHECK: PCRel: 0
@ CHECK: Length: 2
@ CHECK: Type: ARM_RELOC_PAIR (1)
@@ -58,7 +58,7 @@ L2: .long 0
@ CHECK: Section: __data (2)
@ CHECK: }
@ CHECK: Relocation {
-@ CHECK: Offset: 0x1180
+@ CHECK: Offset: 0x400E
@ CHECK: PCRel: 0
@ CHECK: Length: 3
@ CHECK: Type: ARM_RELOC_PAIR (1)
@@ -72,7 +72,7 @@ L2: .long 0
@ CHECK: Section: __data (2)
@ CHECK: }
@ CHECK: Relocation {
-@ CHECK: Offset: 0x1
+@ CHECK: Offset: 0x0
@ CHECK: PCRel: 0
@ CHECK: Length: 2
@ CHECK: Type: ARM_RELOC_PAIR (1)
>From 29f5126562e5d4a77b06df6c0632e16f9172d1af Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Fri, 11 Oct 2024 10:27:18 +0100
Subject: [PATCH 4/4] [DOCS] Add Release Note for change
---
llvm/docs/ReleaseNotes.md | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 8ac5900a7e532e..e5b1e1a37a1b91 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -123,6 +123,11 @@ Changes to the ARM Backend
the required alignment space with a sequence of `0x0` bytes (the requested
fill value) rather than NOPs.
+* When using the `MOVT` or `MOVW` instructions, the Assembler will now check to
+ ensure that any addend that is used is within a 16bit Signed value range. If the
+ addend falls outside of this range, the LLVM backend will emit an error like so
+ `Relocation Not In Range`.
+
Changes to the AVR Backend
--------------------------
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