[llvm] [AMDGPU][MC] Disallow op_sel in v_dot4 and v_dot8 with 4- or 8-bit packed data (PR #100485)
Jun Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 10 18:45:56 PDT 2024
jwanggit86 wrote:
Here's some additional info garnered from the ISA docs.
In RDNA3 doc, Sect 7.1 "Microcode Encodings" there's a statement: "OPSEL may only be used for 16-bit operands, and must be zero for any other operands/results." Since v_dot4_* and v_dot8_* don't operate on 16-bit operands, I think OPSEL is allowed but must be 0.
In RDNA2 doc, Sect 6.2.5 "OPSEL Field Restrictions" states OPSEL is only usable in opcodes listed in Table 21, which doesn't include v_dot4_* or v_dot8_.
In MI300 doc, Sect 6.2.1 "Instruction Inputs" has a statement: "DOT instructions must not use SDWA or OPSEL.".
In MI200 doc, not explicit statements about OPSEL in Dot.
Based on the above, I'd suggest that for v_dot4_* and v_dot8_*, (1) OPSEL should be disallowed for MI300 and RDNA2 (2) OPSEL is allowed but must be 0 for RDNA3.
@arsenm @Sisyph @DadSchoorse Pls let me know your thoughts.
https://github.com/llvm/llvm-project/pull/100485
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