[llvm] [SPIRV] Add GroupMemoryBarrierWithGroupSync intrinsic (PR #111888)
Adam Yang via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 10 13:19:51 PDT 2024
https://github.com/adam-yang updated https://github.com/llvm/llvm-project/pull/111888
>From f071e6d1a46e352316903a202423322f70fc222e Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-yang at users.noreply.github.com>
Date: Tue, 8 Oct 2024 18:55:33 -0700
Subject: [PATCH 1/2] Spirv kind of works now
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 1 +
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 11 +++++++++++
.../GroupMemoryBarrierWithGroupSync.ll | 9 +++++++++
3 files changed, 21 insertions(+)
create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/GroupMemoryBarrierWithGroupSync.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 92d2f67399d263..069d2a45d0ee14 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -85,6 +85,7 @@ let TargetPrefix = "spv" in {
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
+ def int_spv_groupMemoryBarrierWithGroupSync : DefaultAttrsIntrinsic<[], [], []>;
// Create resource handle given the binding information. Returns a
// type appropriate for the kind of resource given the set id, binding id,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index e8b769b6fd6900..66983bb1d54148 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2521,6 +2521,17 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt);
case Intrinsic::spv_sign:
return selectSign(ResVReg, ResType, I);
+ case Intrinsic::spv_groupMemoryBarrierWithGroupSync: {
+ Register MemSemReg = buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I);
+ Register ScopeReg = buildI32Constant(SPIRV::Scope::Workgroup, I);
+ MachineBasicBlock &BB = *I.getParent();
+ return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier))
+ .addUse(ScopeReg)
+ .addUse(ScopeReg)
+ .addUse(MemSemReg)
+ .constrainAllUses(TII, TRI, RBI);
+ //return selectBarrier(ResVReg, ResType, I, SPIRV::OpControlBarrier, );
+ } break;
case Intrinsic::spv_lifetime_start:
case Intrinsic::spv_lifetime_end: {
unsigned Op = IID == Intrinsic::spv_lifetime_start ? SPIRV::OpLifetimeStart
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/GroupMemoryBarrierWithGroupSync.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/GroupMemoryBarrierWithGroupSync.ll
new file mode 100644
index 00000000000000..10185a5356bc5c
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/GroupMemoryBarrierWithGroupSync.ll
@@ -0,0 +1,9 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+define void @test_group_memory_barrier_with_group_sync() {
+entry:
+ ; CHECK: call void @dx.op.barrier(i32 80, i32 9)
+ call void @llvm.spv.groupMemoryBarrierWithGroupSync()
+ ret void
+}
>From 051ce26cbbbb4959bd06fcf7d2cbdc140923d6b5 Mon Sep 17 00:00:00 2001
From: Adam Yang <hanbyang at microsoft.com>
Date: Thu, 10 Oct 2024 12:11:53 -0700
Subject: [PATCH 2/2] Fixed test and updated naming convention for the
intrinsic
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 2 +-
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 6 +++---
.../GroupMemoryBarrierWithGroupSync.ll | 9 ---------
.../group_memory_barrier_with_group_sync.ll | 14 ++++++++++++++
4 files changed, 18 insertions(+), 13 deletions(-)
delete mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/GroupMemoryBarrierWithGroupSync.ll
create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 069d2a45d0ee14..7742808ec059da 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -85,7 +85,7 @@ let TargetPrefix = "spv" in {
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
- def int_spv_groupMemoryBarrierWithGroupSync : DefaultAttrsIntrinsic<[], [], []>;
+ def int_spv_group_memory_barrier_with_group_sync : DefaultAttrsIntrinsic<[], [], []>;
// Create resource handle given the binding information. Returns a
// type appropriate for the kind of resource given the set id, binding id,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 66983bb1d54148..ff52ad87dc9c1f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2521,8 +2521,9 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt);
case Intrinsic::spv_sign:
return selectSign(ResVReg, ResType, I);
- case Intrinsic::spv_groupMemoryBarrierWithGroupSync: {
- Register MemSemReg = buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I);
+ case Intrinsic::spv_group_memory_barrier_with_group_sync: {
+ Register MemSemReg =
+ buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I);
Register ScopeReg = buildI32Constant(SPIRV::Scope::Workgroup, I);
MachineBasicBlock &BB = *I.getParent();
return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier))
@@ -2530,7 +2531,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
.addUse(ScopeReg)
.addUse(MemSemReg)
.constrainAllUses(TII, TRI, RBI);
- //return selectBarrier(ResVReg, ResType, I, SPIRV::OpControlBarrier, );
} break;
case Intrinsic::spv_lifetime_start:
case Intrinsic::spv_lifetime_end: {
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/GroupMemoryBarrierWithGroupSync.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/GroupMemoryBarrierWithGroupSync.ll
deleted file mode 100644
index 10185a5356bc5c..00000000000000
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/GroupMemoryBarrierWithGroupSync.ll
+++ /dev/null
@@ -1,9 +0,0 @@
-; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
-; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-
-define void @test_group_memory_barrier_with_group_sync() {
-entry:
- ; CHECK: call void @dx.op.barrier(i32 80, i32 9)
- call void @llvm.spv.groupMemoryBarrierWithGroupSync()
- ret void
-}
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll
new file mode 100644
index 00000000000000..6955411a0e4e99
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll
@@ -0,0 +1,14 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; CHECK: OpMemoryModel Logical GLSL450
+
+define void @test_group_memory_barrier_with_group_sync() {
+entry:
+ ; CHECK: %[[#TY:]] = OpTypeInt 32 0
+ ; CHECK-DAG: %[[#MEM_SEM:]] = OpConstant %[[#TY]] 16
+ ; CHECK-DAG: %[[#EXEC_AND_MEM_SCOPE:]] = OpConstant %[[#TY]] 2
+ ; CHECK: OpControlBarrier %[[#EXEC_AND_MEM_SCOPE]] %[[#EXEC_AND_MEM_SCOPE]] %[[#MEM_SEM]]
+ call void @llvm.spv.group.memory.barrier.with.group.sync()
+ ret void
+}
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