[llvm] MTM: improve operand latency when missing sched info (PR #101389)

[Ramkumar Ramachandra via llvm-commits]

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@@ -124,10 +124,10 @@ define i64 @scalar_i64(i64 %x, i64 %y, ptr %divdst) nounwind {
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ebp
-; X86-NEXT:    pushl %ebp
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ebx
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artagnon wrote:

After #111865, there should be no changes in the X86 tests except in early-ifcvt-remarks.ll, which already specifies an mcpu that doesn't have scheduling information for all the instructions used. I'm not sure what we can do about the RISCV tests though: the only models available in the tree are SiFive's and Syntacore's; in practice, RISCV is very diverse, and there are lots of scheduling models downstream, so I think we'll have to live with those test changes. 

https://github.com/llvm/llvm-project/pull/101389