[llvm] [RISCV] Add DAG combine to turn (sub (shl X, 8-Y), (shr X, Y)) into orc.b (PR #111828)

[Craig Topper via llvm-commits]

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@@ -13587,18 +13589,45 @@ static SDValue combineSubShiftToOrcB(SDNode *N, SelectionDAG &DAG,
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
 
-  if (N0.getOpcode() != ISD::SHL || N0.getOperand(0) != N1 || !N0.hasOneUse())
+  if (N0->getOpcode() != ISD::SHL)
+    return SDValue();
+  
+  auto *ShAmtCLeft = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+  if (!ShAmtCLeft)
+    return SDValue();
+  unsigned ShiftedAmount = 8 - ShAmtCLeft->getZExtValue();
+
+  if (ShiftedAmount >= 8)
+    return SDValue();
+
+  SDValue LeftShiftOperand = N0->getOperand(0);
+  SDValue RightShiftOperand = N1;
+
+  if (ShiftedAmount != 0 && N1->getOpcode() != ISD::SRL)
+    return SDValue();
+
+  if (ShiftedAmount != 0) { // Right operand must be a right shift.
+    auto *ShAmtCRight = dyn_cast<ConstantSDNode>(N1.getOperand(1));
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topperc wrote:

Move the `N1->getOpcode() != ISD::SRL` check into this if?

https://github.com/llvm/llvm-project/pull/111828