[llvm] [RISCV][RFC] Enable store clustering by default (PR #73796)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 10 07:29:36 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Alex Bradbury (asb)
<details>
<summary>Changes</summary>
Builds on #<!-- -->73789, enabling store clustering by default using the same heuristic. It's not clear if this is desirable, but posting in case anyone has views. As it's stacked on other in-review PRs, you'll want to just look at the most recent commit to see how it impacts the in-tree tests.
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Patch is 1.51 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73796.diff
249 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll (+21-21)
- (modified) llvm/test/CodeGen/RISCV/abds-neg.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/abds.ll (+74-74)
- (modified) llvm/test/CodeGen/RISCV/abdu-neg.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/add-before-shl.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/alloca.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll (+20-20)
- (modified) llvm/test/CodeGen/RISCV/callee-saved-gprs.ll (+56-56)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll (+36-36)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll (+88-88)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll (+256-256)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll (+40-40)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll (+5-4)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll (+11-10)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/calls.ll (+12-12)
- (modified) llvm/test/CodeGen/RISCV/double-calling-conv.ll (+14-14)
- (modified) llvm/test/CodeGen/RISCV/double-convert-strict.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/double-convert.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/fastcc-bf16.ll (+9-9)
- (modified) llvm/test/CodeGen/RISCV/fastcc-float.ll (+9-9)
- (modified) llvm/test/CodeGen/RISCV/fastcc-half.ll (+9-9)
- (modified) llvm/test/CodeGen/RISCV/fastcc-int.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll (+404-404)
- (modified) llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/forced-atomics.ll (+29-29)
- (modified) llvm/test/CodeGen/RISCV/fp128.ll (+34-34)
- (modified) llvm/test/CodeGen/RISCV/frame.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/get-setcc-result-type.ll (+3-3)
- (modified) llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/legalize-fneg.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/llvm.exp10.ll (+27-27)
- (modified) llvm/test/CodeGen/RISCV/llvm.frexp.ll (+234-234)
- (modified) llvm/test/CodeGen/RISCV/memcpy.ll (+87-87)
- (modified) llvm/test/CodeGen/RISCV/memset-inline.ll (+517-517)
- (modified) llvm/test/CodeGen/RISCV/neg-abs.ll (+6-4)
- (modified) llvm/test/CodeGen/RISCV/nontemporal.ll (+1480-1480)
- (modified) llvm/test/CodeGen/RISCV/overflow-intrinsics.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/pr63816.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/push-pop-popret.ll (+27-27)
- (modified) llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rv32zbb.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/binop-splats.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll (+11-11)
- (modified) llvm/test/CodeGen/RISCV/rvv/combine-store.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll (+22-22)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll (+3-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll (+48-48)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll (+56-83)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll (+48-48)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll (+176-176)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll (+24-24)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll (+33-33)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll (+3-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll (+70-70)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll (+64-64)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll (+260-260)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll (+66-66)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll (+16-16)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll (+18-18)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll (+16-16)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll (+24-24)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll (+9-9)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll (+9-9)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll (+7-7)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll (+3-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll (+7-7)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll (+180-180)
- (modified) llvm/test/CodeGen/RISCV/rvv/masked-tama.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/memset-inline.ll (+44-44)
- (modified) llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/pr104480.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll (+36-36)
- (modified) llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll (+20-20)
- (modified) llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/stepvector.ll (+17-17)
- (modified) llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll (+5-5)
- (modified) llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll (+9-9)
- (modified) llvm/test/CodeGen/RISCV/rvv/vaadd.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/vaaddu.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vadc.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll (+5-5)
- (modified) llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vadd.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll (+5-5)
- (modified) llvm/test/CodeGen/RISCV/rvv/vand-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vand.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll (+16-16)
- (modified) llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vandn.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vasub.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vasubu.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vclmul.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vclmulh.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll (+16-16)
- (modified) llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vdiv.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll (+12-12)
- (modified) llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vdivu.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll (+12-12)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmacc.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmadc.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll (+12-12)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmadd.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmax.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmaxu.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmin.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vminu.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmsbc.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmseq.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmsge.ll (+9-9)
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- (modified) llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll (+2-2)
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- (modified) llvm/test/CodeGen/RISCV/srem-vector-lkk.ll (+115-115)
- (modified) llvm/test/CodeGen/RISCV/stack-slot-size.ll (+16-16)
- (modified) llvm/test/CodeGen/RISCV/stack-store-check.ll (+243-241)
- (modified) llvm/test/CodeGen/RISCV/tail-calls.ll (+16-16)
- (modified) llvm/test/CodeGen/RISCV/unaligned-load-store.ll (+70-70)
- (modified) llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll (+18-18)
- (modified) llvm/test/CodeGen/RISCV/urem-vector-lkk.ll (+108-108)
- (modified) llvm/test/CodeGen/RISCV/vararg-ilp32e.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/vararg.ll (+526-526)
- (modified) llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll (+1764-1758)
- (modified) llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll (+648-648)
- (modified) llvm/test/CodeGen/RISCV/xtheadmempair.ll (+2-2)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 2dcac1320417c2..0d05bd06eba2e4 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -351,6 +351,8 @@ class RISCVPassConfig : public TargetPassConfig {
DAG = createGenericSchedLive(C);
DAG->addMutation(createLoadClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+ DAG->addMutation(createStoreClusterDAGMutation(
+ DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
}
return DAG;
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
index 3df4aca40ec942..6c0e322a252c72 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
@@ -69,12 +69,12 @@ define i32 @va1(ptr %fmt, ...) {
; RV64-NEXT: sd a2, 32(sp)
; RV64-NEXT: sd a3, 40(sp)
; RV64-NEXT: sd a4, 48(sp)
-; RV64-NEXT: sd a5, 56(sp)
; RV64-NEXT: addi a0, sp, 8
; RV64-NEXT: addi a1, sp, 24
; RV64-NEXT: sd a1, 8(sp)
; RV64-NEXT: lw a0, 4(a0)
; RV64-NEXT: lwu a1, 8(sp)
+; RV64-NEXT: sd a5, 56(sp)
; RV64-NEXT: sd a6, 64(sp)
; RV64-NEXT: sd a7, 72(sp)
; RV64-NEXT: slli a0, a0, 32
@@ -129,12 +129,12 @@ define i32 @va1(ptr %fmt, ...) {
; RV64-WITHFP-NEXT: sd a2, 16(s0)
; RV64-WITHFP-NEXT: sd a3, 24(s0)
; RV64-WITHFP-NEXT: sd a4, 32(s0)
-; RV64-WITHFP-NEXT: sd a5, 40(s0)
; RV64-WITHFP-NEXT: addi a0, s0, -24
; RV64-WITHFP-NEXT: addi a1, s0, 8
; RV64-WITHFP-NEXT: sd a1, -24(s0)
; RV64-WITHFP-NEXT: lw a0, 4(a0)
; RV64-WITHFP-NEXT: lwu a1, -24(s0)
+; RV64-WITHFP-NEXT: sd a5, 40(s0)
; RV64-WITHFP-NEXT: sd a6, 48(s0)
; RV64-WITHFP-NEXT: sd a7, 56(s0)
; RV64-WITHFP-NEXT: slli a0, a0, 32
@@ -844,11 +844,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; ILP32-LABEL: va3:
; ILP32: # %bb.0:
; ILP32-NEXT: addi sp, sp, -32
-; ILP32-NEXT: sw a3, 12(sp)
-; ILP32-NEXT: sw a4, 16(sp)
; ILP32-NEXT: addi a0, sp, 12
; ILP32-NEXT: sw a0, 4(sp)
; ILP32-NEXT: lw a0, 4(sp)
+; ILP32-NEXT: sw a3, 12(sp)
+; ILP32-NEXT: sw a4, 16(sp)
; ILP32-NEXT: sw a5, 20(sp)
; ILP32-NEXT: sw a6, 24(sp)
; ILP32-NEXT: sw a7, 28(sp)
@@ -868,11 +868,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV32D-ILP32-LABEL: va3:
; RV32D-ILP32: # %bb.0:
; RV32D-ILP32-NEXT: addi sp, sp, -48
-; RV32D-ILP32-NEXT: sw a3, 28(sp)
-; RV32D-ILP32-NEXT: sw a4, 32(sp)
; RV32D-ILP32-NEXT: addi a0, sp, 28
; RV32D-ILP32-NEXT: sw a0, 20(sp)
; RV32D-ILP32-NEXT: lw a0, 20(sp)
+; RV32D-ILP32-NEXT: sw a3, 28(sp)
+; RV32D-ILP32-NEXT: sw a4, 32(sp)
; RV32D-ILP32-NEXT: sw a5, 36(sp)
; RV32D-ILP32-NEXT: sw a6, 40(sp)
; RV32D-ILP32-NEXT: sw a7, 44(sp)
@@ -894,11 +894,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV32D-ILP32F-LABEL: va3:
; RV32D-ILP32F: # %bb.0:
; RV32D-ILP32F-NEXT: addi sp, sp, -48
-; RV32D-ILP32F-NEXT: sw a3, 28(sp)
-; RV32D-ILP32F-NEXT: sw a4, 32(sp)
; RV32D-ILP32F-NEXT: addi a0, sp, 28
; RV32D-ILP32F-NEXT: sw a0, 20(sp)
; RV32D-ILP32F-NEXT: lw a0, 20(sp)
+; RV32D-ILP32F-NEXT: sw a3, 28(sp)
+; RV32D-ILP32F-NEXT: sw a4, 32(sp)
; RV32D-ILP32F-NEXT: sw a5, 36(sp)
; RV32D-ILP32F-NEXT: sw a6, 40(sp)
; RV32D-ILP32F-NEXT: sw a7, 44(sp)
@@ -920,11 +920,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV32D-ILP32D-LABEL: va3:
; RV32D-ILP32D: # %bb.0:
; RV32D-ILP32D-NEXT: addi sp, sp, -48
-; RV32D-ILP32D-NEXT: sw a3, 28(sp)
-; RV32D-ILP32D-NEXT: sw a4, 32(sp)
; RV32D-ILP32D-NEXT: addi a0, sp, 28
; RV32D-ILP32D-NEXT: sw a0, 20(sp)
; RV32D-ILP32D-NEXT: lw a0, 20(sp)
+; RV32D-ILP32D-NEXT: sw a3, 28(sp)
+; RV32D-ILP32D-NEXT: sw a4, 32(sp)
; RV32D-ILP32D-NEXT: sw a5, 36(sp)
; RV32D-ILP32D-NEXT: sw a6, 40(sp)
; RV32D-ILP32D-NEXT: sw a7, 44(sp)
@@ -946,12 +946,12 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV64-LABEL: va3:
; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -64
-; RV64-NEXT: sd a2, 16(sp)
-; RV64-NEXT: sd a3, 24(sp)
-; RV64-NEXT: sd a4, 32(sp)
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: sd a0, 8(sp)
; RV64-NEXT: ld a0, 8(sp)
+; RV64-NEXT: sd a2, 16(sp)
+; RV64-NEXT: sd a3, 24(sp)
+; RV64-NEXT: sd a4, 32(sp)
; RV64-NEXT: sd a5, 40(sp)
; RV64-NEXT: sd a6, 48(sp)
; RV64-NEXT: sd a7, 56(sp)
@@ -970,11 +970,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV32-WITHFP-NEXT: sw ra, 20(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 16(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: addi s0, sp, 24
-; RV32-WITHFP-NEXT: sw a3, 4(s0)
-; RV32-WITHFP-NEXT: sw a4, 8(s0)
; RV32-WITHFP-NEXT: addi a0, s0, 4
; RV32-WITHFP-NEXT: sw a0, -12(s0)
; RV32-WITHFP-NEXT: lw a0, -12(s0)
+; RV32-WITHFP-NEXT: sw a3, 4(s0)
+; RV32-WITHFP-NEXT: sw a4, 8(s0)
; RV32-WITHFP-NEXT: sw a5, 12(s0)
; RV32-WITHFP-NEXT: sw a6, 16(s0)
; RV32-WITHFP-NEXT: sw a7, 20(s0)
@@ -999,12 +999,12 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV64-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: addi s0, sp, 32
-; RV64-WITHFP-NEXT: sd a2, 0(s0)
-; RV64-WITHFP-NEXT: sd a3, 8(s0)
-; RV64-WITHFP-NEXT: sd a4, 16(s0)
; RV64-WITHFP-NEXT: mv a0, s0
; RV64-WITHFP-NEXT: sd a0, -24(s0)
; RV64-WITHFP-NEXT: ld a0, -24(s0)
+; RV64-WITHFP-NEXT: sd a2, 0(s0)
+; RV64-WITHFP-NEXT: sd a3, 8(s0)
+; RV64-WITHFP-NEXT: sd a4, 16(s0)
; RV64-WITHFP-NEXT: sd a5, 24(s0)
; RV64-WITHFP-NEXT: sd a6, 32(s0)
; RV64-WITHFP-NEXT: sd a7, 40(s0)
@@ -1622,9 +1622,6 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV64-NEXT: lui a0, 24414
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: sd a4, 304(a0)
-; RV64-NEXT: lui a0, 24414
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: sd a5, 312(a0)
; RV64-NEXT: addi a0, sp, 8
; RV64-NEXT: lui a1, 24414
; RV64-NEXT: addiw a1, a1, 280
@@ -1634,6 +1631,9 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV64-NEXT: lwu a1, 8(sp)
; RV64-NEXT: lui a2, 24414
; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: sd a5, 312(a2)
+; RV64-NEXT: lui a2, 24414
+; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: sd a6, 320(a2)
; RV64-NEXT: lui a2, 24414
; RV64-NEXT: add a2, sp, a2
diff --git a/llvm/test/CodeGen/RISCV/abds-neg.ll b/llvm/test/CodeGen/RISCV/abds-neg.ll
index b6064198935a61..e7fd87bd783876 100644
--- a/llvm/test/CodeGen/RISCV/abds-neg.ll
+++ b/llvm/test/CodeGen/RISCV/abds-neg.ll
@@ -705,8 +705,8 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sub a4, a4, a3
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sw a1, 0(a0)
-; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a2, 4(a0)
+; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a5, 12(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -824,8 +824,8 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sub a4, a4, a3
; RV32ZBB-NEXT: neg a1, a1
; RV32ZBB-NEXT: sw a1, 0(a0)
-; RV32ZBB-NEXT: sw a4, 8(a0)
; RV32ZBB-NEXT: sw a2, 4(a0)
+; RV32ZBB-NEXT: sw a4, 8(a0)
; RV32ZBB-NEXT: sw a5, 12(a0)
; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: addi sp, sp, 16
@@ -952,8 +952,8 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sub a4, a4, a3
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sw a1, 0(a0)
-; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a2, 4(a0)
+; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a5, 12(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -1071,8 +1071,8 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sub a4, a4, a3
; RV32ZBB-NEXT: neg a1, a1
; RV32ZBB-NEXT: sw a1, 0(a0)
-; RV32ZBB-NEXT: sw a4, 8(a0)
; RV32ZBB-NEXT: sw a2, 4(a0)
+; RV32ZBB-NEXT: sw a4, 8(a0)
; RV32ZBB-NEXT: sw a5, 12(a0)
; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: addi sp, sp, 16
@@ -1918,9 +1918,9 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sub a1, a1, t2
; RV32I-NEXT: sub a2, a2, a3
; RV32I-NEXT: .LBB22_11:
-; RV32I-NEXT: sw a6, 8(a0)
-; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: sw a2, 0(a0)
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: sw a6, 8(a0)
; RV32I-NEXT: sw a5, 12(a0)
; RV32I-NEXT: ret
;
@@ -2005,9 +2005,9 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sub a1, a1, t2
; RV32ZBB-NEXT: sub a2, a2, a3
; RV32ZBB-NEXT: .LBB22_11:
-; RV32ZBB-NEXT: sw a6, 8(a0)
-; RV32ZBB-NEXT: sw a1, 4(a0)
; RV32ZBB-NEXT: sw a2, 0(a0)
+; RV32ZBB-NEXT: sw a1, 4(a0)
+; RV32ZBB-NEXT: sw a6, 8(a0)
; RV32ZBB-NEXT: sw a5, 12(a0)
; RV32ZBB-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/abds.ll b/llvm/test/CodeGen/RISCV/abds.ll
index 91b044902a5201..e639d4b30d4c94 100644
--- a/llvm/test/CodeGen/RISCV/abds.ll
+++ b/llvm/test/CodeGen/RISCV/abds.ll
@@ -599,9 +599,9 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sub a1, a4, t5
; RV32I-NEXT: sub a4, a6, t6
; RV32I-NEXT: .LBB11_13:
-; RV32I-NEXT: sw a4, 8(a0)
-; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: sw a3, 0(a0)
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -695,9 +695,9 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sub a1, a4, t5
; RV32ZBB-NEXT: sub a4, a6, t6
; RV32ZBB-NEXT: .LBB11_13:
-; RV32ZBB-NEXT: sw a4, 8(a0)
-; RV32ZBB-NEXT: sw a1, 4(a0)
; RV32ZBB-NEXT: sw a3, 0(a0)
+; RV32ZBB-NEXT: sw a1, 4(a0)
+; RV32ZBB-NEXT: sw a4, 8(a0)
; RV32ZBB-NEXT: sw a2, 12(a0)
; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: addi sp, sp, 16
@@ -799,9 +799,9 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sub a1, a4, t5
; RV32I-NEXT: sub a4, a6, t6
; RV32I-NEXT: .LBB12_13:
-; RV32I-NEXT: sw a4, 8(a0)
-; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: sw a3, 0(a0)
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -895,9 +895,9 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sub a1, a4, t5
; RV32ZBB-NEXT: sub a4, a6, t6
; RV32ZBB-NEXT: .LBB12_13:
-; RV32ZBB-NEXT: sw a4, 8(a0)
-; RV32ZBB-NEXT: sw a1, 4(a0)
; RV32ZBB-NEXT: sw a3, 0(a0)
+; RV32ZBB-NEXT: sw a1, 4(a0)
+; RV32ZBB-NEXT: sw a4, 8(a0)
; RV32ZBB-NEXT: sw a2, 12(a0)
; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: addi sp, sp, 16
@@ -1188,9 +1188,9 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sub a1, a4, t5
; RV32I-NEXT: sub a4, a6, t6
; RV32I-NEXT: .LBB17_13:
-; RV32I-NEXT: sw a4, 8(a0)
-; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: sw a3, 0(a0)
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -1284,9 +1284,9 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sub a1, a4, t5
; RV32ZBB-NEXT: sub a4, a6, t6
; RV32ZBB-NEXT: .LBB17_13:
-; RV32ZBB-NEXT: sw a4, 8(a0)
-; RV32ZBB-NEXT: sw a1, 4(a0)
; RV32ZBB-NEXT: sw a3, 0(a0)
+; RV32ZBB-NEXT: sw a1, 4(a0)
+; RV32ZBB-NEXT: sw a4, 8(a0)
; RV32ZBB-NEXT: sw a2, 12(a0)
; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: addi sp, sp, 16
@@ -1579,9 +1579,9 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sub a1, a4, t5
; RV32I-NEXT: sub a4, a6, t6
; RV32I-NEXT: .LBB22_13:
-; RV32I-NEXT: sw a4, 8(a0)
-; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: sw a3, 0(a0)
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -1675,9 +1675,9 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: sub a1, a4, t5
; RV32ZBB-NEXT: sub a4, a6, t6
; RV32ZBB-NEXT: .LBB22_13:
-; RV32ZBB-NEXT: sw a4, 8(a0)
-; RV32ZBB-NEXT: sw a1, 4(a0)
; RV32ZBB-NEXT: sw a3, 0(a0)
+; RV32ZBB-NEXT: sw a1, 4(a0)
+; RV32ZBB-NEXT: sw a4, 8(a0)
; RV32ZBB-NEXT: sw a2, 12(a0)
; RV32ZBB-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: addi sp, sp, 16
@@ -2043,8 +2043,8 @@ define i64 @abd_subnsw_i64_undef(i64 %a, i64 %b) nounwind {
define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_subnsw_i128:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a2)
-; RV32I-NEXT: lw a4, 4(a2)
+; RV32I-NEXT: lw a4, 0(a2)
+; RV32I-NEXT: lw a3, 4(a2)
; RV32I-NEXT: lw a6, 8(a2)
; RV32I-NEXT: lw t0, 12(a2)
; RV32I-NEXT: lw a2, 8(a1)
@@ -2053,24 +2053,24 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: lw a7, 4(a1)
; RV32I-NEXT: sltu a1, a2, a6
; RV32I-NEXT: sub t1, t1, t0
-; RV32I-NEXT: sltu t0, a5, a3
+; RV32I-NEXT: sltu t0, a5, a4
; RV32I-NEXT: sub a1, t1, a1
; RV32I-NEXT: mv t1, t0
-; RV32I-NEXT: beq a7, a4, .LBB31_2
+; RV32I-NEXT: beq a7, a3, .LBB31_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltu t1, a7, a4
+; RV32I-NEXT: sltu t1, a7, a3
; RV32I-NEXT: .LBB31_2:
; RV32I-NEXT: sub a2, a2, a6
; RV32I-NEXT: sltu a6, a2, t1
; RV32I-NEXT: sub a1, a1, a6
; RV32I-NEXT: sub a2, a2, t1
-; RV32I-NEXT: sub a4, a7, a4
-; RV32I-NEXT: sub a4, a4, t0
-; RV32I-NEXT: sub a3, a5, a3
+; RV32I-NEXT: sub a3, a7, a3
+; RV32I-NEXT: sub a3, a3, t0
+; RV32I-NEXT: sub a4, a5, a4
; RV32I-NEXT: bgez a1, .LBB31_4
; RV32I-NEXT: # %bb.3:
-; RV32I-NEXT: snez a5, a4
-; RV32I-NEXT: snez a6, a3
+; RV32I-NEXT: snez a5, a3
+; RV32I-NEXT: snez a6, a4
; RV32I-NEXT: or a5, a6, a5
; RV32I-NEXT: neg a7, a2
; RV32I-NEXT: sltu t0, a7, a5
@@ -2079,12 +2079,12 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, t0
; RV32I-NEXT: sub a2, a7, a5
-; RV32I-NEXT: neg a3, a3
-; RV32I-NEXT: add a4, a4, a6
; RV32I-NEXT: neg a4, a4
+; RV32I-NEXT: add a3, a3, a6
+; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: .LBB31_4:
-; RV32I-NEXT: sw a4, 4(a0)
-; RV32I-NEXT: sw a3, 0(a0)
+; RV32I-NEXT: sw a4, 0(a0)
+; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a2, 8(a0)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: ret
@@ -2106,8 +2106,8 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_subnsw_i128:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a2)
-; RV32ZBB-NEXT: lw a4, 4(a2)
+; RV32ZBB-NEXT: lw a4, 0(a2)
+; RV32ZBB-NEXT: lw a3, 4(a2)
; RV32ZBB-NEXT: lw a6, 8(a2)
; RV32ZBB-NEXT: lw t0, 12(a2)
; RV32ZBB-NEXT: lw a2, 8(a1)
@@ -2116,24 +2116,24 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: lw a7, 4(a1)
; RV32ZBB-NEXT: sltu a1, a2, a6
; RV32ZBB-NEXT: sub t1, t1, t0
-; RV32ZBB-NEXT: sltu t0, a5, a3
+; RV32ZBB-NEXT: sltu t0, a5, a4
; RV32ZBB-NEXT: sub a1, t1, a1
; RV32ZBB-NEXT: mv t1, t0
-; RV32ZBB-NEXT: beq a7, a4, .LBB31_2
+; RV32ZBB-NEXT: beq a7, a3, .LBB31_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: sltu t1, a7, a4
+; RV32ZBB-NEXT: sltu t1, a7, a3
; RV32ZBB-NEXT: .LBB31_2:
; RV32ZBB-NEXT: sub a2, a2, a6
; RV32ZBB-NEXT: sltu a6, a2, t1
; RV32ZBB-NEXT: sub a1, a1, a6
; RV32ZBB-NEXT: sub a2, a2, t1
-; RV32ZBB-NEXT: sub a4, a7, a4
-; RV32ZBB-NEXT: sub a4, a4, t0
-; RV32ZBB-NEXT: sub a3, a5, a3
+; RV32ZBB-NEXT: sub a3, a7, a3
+; RV32ZBB-NEXT: sub a3, a3, t0
+; RV32ZBB-NEXT: sub a4, a5, a4
; RV32ZBB-NEXT: bgez a1, .LBB31_4
; RV32ZBB-NEXT: # %bb.3:
-; RV32ZBB-NEXT: snez a5, a4
-; RV32ZBB-NEXT: snez a6, a3
+; RV32ZBB-NEXT: snez a5, a3
+; RV32ZBB-NEXT: snez a6, a4
; RV32ZBB-NEXT: or a5, a6, a5
; RV32ZBB-NEXT: neg a7, a2
; RV32ZBB-NEXT: sltu t0, a7, a5
@@ -2142,12 +2142,12 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: neg a1, a1
; RV32ZBB-NEXT: sub a1, a1, t0
; RV32ZBB-NEXT: sub a2, a7, a5
-; RV32ZBB-NEXT: neg a3, a3
-; RV32ZBB-NEXT: add a4, a4, a6
; RV32ZBB-NEXT: neg a4, a4
+; RV32ZBB-NEXT: add a3, a3, a6
+; RV32ZBB-NEXT: neg a3, a3
; RV32ZBB-NEXT: .LBB31_4:
-; RV32ZBB-NEXT: sw a4, 4(a0)
-; RV32ZBB-NEXT: sw a3, 0(a0)
+; RV32ZBB-NEXT: sw a4, 0(a0)
+; RV32ZBB-NEXT: sw a3, 4(a0)
; RV32ZBB-NEXT: sw a2, 8(a0)
; RV32ZBB-NEXT: sw a1, 12(a0)
; RV32ZBB-NEXT: ret
@@ -2174,8 +2174,8 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: abd_subnsw_i128_undef:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 0(a2)
-; RV32I-NEXT: lw a4, 4(a2)
+; RV32I-NEXT: lw a4, 0(a2)
+; RV32I-NEXT: lw a3, 4(a2)
; RV32I-NEXT: lw a6, 8(a2)
; RV32I-NEXT: lw t0, 12(a2)
; RV32I-NEXT: lw a2, 8(a1)
@@ -2184,24 +2184,24 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: lw a7, 4(a1)
; RV32I-NEXT: sltu a1, a2, a6
; RV32I-NEXT: sub t1, t1, t0
-; RV32I-NEXT: sltu t0, a5, a3
+; RV32I-NEXT: sltu t0, a5, a4
; RV32I-NEXT: sub a1, t1, a1
; RV32I-NEXT: mv t1, t0
-; RV32I-NEXT: beq a7, a4, .LBB32_2
+; RV32I-NEXT: beq a7, a3, .LBB32_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: sltu t1, a7, a4
+; RV32I-NEXT: sltu t1, a7, a3
; RV32I-NEXT: .LBB32_2:
; RV32I-NEXT: sub a2, a2, a6
; RV32I-NEXT: sltu a6, a2, t1
; RV32I-NEXT: sub a1, a1, a6
; RV32I-NEXT: sub a2, a2, t1
-; RV32I-NEXT: sub a4, a7, a4
-; RV32I-NEXT: sub a4, a4, t0
-; RV32I-NEXT: sub a3, a5, a3
+; RV32I-NEXT: sub a3, a7, a3
+; RV32I-NEXT: sub a3, a3, t0
+; RV32I-NEXT: sub a4, a5, a4
; RV32I-NEXT: bgez a1, .LBB32_4
; RV32I-NEXT: # %bb.3:
-; RV32I-NEXT: snez a5, a4
-; RV32I-NEXT: snez a6, a3
+; RV32I-NEXT: snez a5, a3
+; RV32I-NEXT: snez a6, a4
; RV32I-NEXT: or a5, a6, a5
; RV32I-NEXT: neg a7, a2
; RV32I-NEXT: sltu t0, a7, a5
@@ -2210,12 +2210,12 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, t0
; RV32I-NEXT: sub a2, a7, a5
-; RV32I-NEXT: neg a3, a3
-; RV32I-NEXT: add a4, a4, a6
; RV32I-NEXT: neg a4, a4
+; RV32I-NEXT: add a3, a3, a6
+; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: .LBB32_4:
-; RV32I-NEXT: sw a4, 4(a0)
-; RV32I-NEXT: sw a3, 0(a0)
+; RV32I-NEXT: sw a4, 0(a0)
+; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a2, 8(a0)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: ret
@@ -2237,8 +2237,8 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
;
; RV32ZBB-LABEL: abd_subnsw_i128_undef:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: lw a3, 0(a2)
-; RV32ZBB-NEXT: lw a4, 4(a2)
+; RV32ZBB-NEXT: lw a4, 0(a2)
+; RV32ZBB-NEXT: lw a3, 4(a2)
; RV32ZBB-NEXT: lw a6, 8(a2)
; RV32ZBB-NEXT: lw t0, 12(a2)
; RV32ZBB-NEXT: lw a2, 8(a1)
@@ -2247,24 +2247,24 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
; RV32ZBB-NEXT: lw a7, 4(a1)
; RV32ZBB-NEXT: sltu a1, a2, a6
; RV32ZBB-NEXT: sub t1, t1, t0
-; RV32ZBB-NEXT: sltu t0, a5, a3
+; RV32ZBB-NEXT: sltu t0, a5, a4
; RV32ZBB-NEXT: sub a1, t1, a1
; RV32ZBB-NEXT: mv t1, t0
-; RV32ZBB-NEXT: beq a7, a4, .LBB32_2
+; RV32ZBB-NEXT: beq a7, a3, .LBB32_2
; RV32ZBB-NEXT: # %bb.1:
-; RV32ZBB-NEXT: sltu t1, a7, a4
+; RV32ZBB-NEXT: sltu t1, a7, a3
; RV32ZBB-NEXT: .LBB32_2:
; RV32ZBB-NEXT: sub a2, a2, a6
; RV32ZBB-NEXT: sltu a6, a2, t1
; RV32ZBB-NEXT: sub a1, a1, a6
; RV32ZBB-NEXT: sub a2, a2, t1
-; RV32ZBB-NEXT: sub a4, a7, a4
-; RV32ZBB-...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/73796
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