[llvm] dabb0dd - [MCP] Skip invalidating def constant regs during forward propagation (#111129)

[via llvm-commits]

Author: Vladimir Radosavljevic
Date: 2024-10-10T18:05:42+04:00
New Revision: dabb0ddbd7a7229855156c61df1d35ad845361ac

URL: https://github.com/llvm/llvm-project/commit/dabb0ddbd7a7229855156c61df1d35ad845361ac
DIFF: https://github.com/llvm/llvm-project/commit/dabb0ddbd7a7229855156c61df1d35ad845361ac.diff

LOG: [MCP] Skip invalidating def constant regs during forward propagation (#111129)

Before this patch, redundant COPY couldn't be removed for the following
case:
```
  %reg1 = COPY %const-reg
  ... // There is a def of %const-reg
  %reg2 = COPY killed %reg1
```
where this can be optimized to:
```
  ... // There is a def of %const-reg
  %reg2 = COPY %const-reg
```

This patch allows for such optimization by not invalidating defined
constant registers. This is safe, as architectures like AArch64 and
RISCV replace a dead definition of a GPR with a zero constant register
for certain instructions.

Added: 
    llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir

Modified: 
    llvm/lib/CodeGen/MachineCopyPropagation.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 8bcc437cbfb865..fb4da2c11cda77 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -886,8 +886,11 @@ void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) {
              "MachineCopyPropagation should be run after register allocation!");
 
       if (MO.isDef() && !MO.isEarlyClobber()) {
-        Defs.push_back(Reg.asMCReg());
-        continue;
+        // Skip invalidating constant registers.
+        if (!MRI->isConstantPhysReg(Reg)) {
+          Defs.push_back(Reg.asMCReg());
+          continue;
+        }
       } else if (MO.readsReg())
         ReadRegister(Reg.asMCReg(), MI, MO.isDebug() ? DebugUse : RegularUse);
     }

diff  --git a/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir b/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir
new file mode 100644
index 00000000000000..cad55b9daffafd
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir
@@ -0,0 +1,19 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test
+body: |
+  bb.0:
+    liveins: $w2
+    ; CHECK-LABEL: name: test
+    ; CHECK: liveins: $w2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $wzr = SUBSWri killed renamable $w2, 0, 0, implicit-def $nzcv
+    ; CHECK-NEXT: renamable $w0 = COPY $wzr
+    ; CHECK-NEXT: RET_ReallyLR implicit killed $w0
+    renamable $w1 = COPY $wzr
+    $wzr = SUBSWri killed renamable $w2, 0, 0, implicit-def $nzcv
+    renamable $w0 = COPY killed renamable $w1
+    RET_ReallyLR implicit killed $w0
+...