[llvm] [ARM] Fix problems with register list in vscclrm (PR #111825)

[Simon Tatham via llvm-commits]

================
@@ -27,3 +29,36 @@
 
 [0xdf 0xec 0x1d 0x1a]
 # CHECK: vscclrmhi    {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
+
+# If the list size is zero then we get a list of only vpr, and the Vd register
+# doesn't matter.
+
+[0x9f,0xec,0x00,0x0b]
+# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0b]
+
+[0xdf,0xec,0x00,0xfb]
+# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0b]
+
+[0x9f,0xec,0x00,0x0a]
+# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0a]
+
+[0xdf,0xec,0x00,0xfa]
+# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0a]
+
+# If Vd+size goes past 31 the excess registers are ignored and we get a warning.
----------------
statham-arm wrote:

I think VSCCLRM is even more unusual than you say.

Reading the ARMARM for the single-precision version of VSCCLRM, the validity criteria are:
```
topReg = d+regs-1;
if topReg > 63 then UNPREDICTABLE;
if topReg > 31 && topReg[0] == '0' then UNPREDICTABLE;
```
which suggests that you're supposed to be able to go past s31 into the region past the end of the s-registers where d16-d31 live, and continue clearing d-registers, as long as you don't stop half way through one. Confirmed by the text about `<sreglist>`: "Registers above S31 are specified by using D registers in the register list."

I think that, for example, `[0xdf,0xec,0x07,0xea]` ought to disassemble as `vscclrm {s29, s30, s31, d16, d17, vpr}` with no unpredictability warning: clearing 7 s-register sized pieces starting at s29 means you overrun the end of the s regs by 4, i.e. by 2 d-regs.

https://github.com/llvm/llvm-project/pull/111825