[llvm] [AArch64] Add support for Armv9.6-A FEAT_MPAM system registers (PR #111822)
Jonathan Thackray via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 10 05:07:04 PDT 2024
https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/111822
Add support for Armv9.6-A FEAT_MPAM system registers as documented here:
https://developer.arm.com/documentation/ddi0601/2024-09/AArch64-Registers
>From e1f8d5cdeec743372db72ff4cdd8e098cda1d4f7 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Thu, 10 Oct 2024 10:17:48 +0100
Subject: [PATCH] [AArch64] Add support for Armv9.6-A FEAT_MPAM system
registers
Add support for Armv9.6-A FEAT_MPAM system registers as documented here:
https://developer.arm.com/documentation/ddi0601/2024-09/AArch64-Registers
---
.../Target/AArch64/AArch64SystemOperands.td | 11 ++++
llvm/test/MC/AArch64/armv9.6a-mpam.s | 45 +++++++++++++++++
.../MC/Disassembler/AArch64/armv9.6a-mpam.txt | 50 +++++++++++++++++++
3 files changed, 106 insertions(+)
create mode 100644 llvm/test/MC/AArch64/armv9.6a-mpam.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index dd0ce1cf47a792..474a543a857494 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1970,3 +1970,14 @@ def : RWSysReg<"HACDBSCONS_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b101>;
// v9.5a Fine Grained Write Trap EL3 (FEAT_FGWTE3)
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"FGWTE3_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b101>;
+
+// v9.6a Memory partitioning and monitoring (FEAT_MPAM) registers
+// Op0 Op1 CRn CRm Op2
+def : ROSysReg<"MPAMBWIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b101>;
+def : RWSysReg<"MPAMBW3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b101>;
+def : RWSysReg<"MPAMBWCAP_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b110>;
+def : RWSysReg<"MPAMBWSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b111>;
diff --git a/llvm/test/MC/AArch64/armv9.6a-mpam.s b/llvm/test/MC/AArch64/armv9.6a-mpam.s
new file mode 100644
index 00000000000000..c0696efd3ccebb
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.6a-mpam.s
@@ -0,0 +1,45 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK
+// RUN: FileCheck --check-prefix=CHECK-RO < %t %s
+
+//------------------------------------------------------------------------------
+// Armv9.6-A FEAT_MPAM Extensions
+//------------------------------------------------------------------------------
+
+msr MPAMBWIDR_EL1, x0
+msr MPAMBW3_EL3, x0
+msr MPAMBW2_EL2, x0
+msr MPAMBW1_EL1, x0
+msr MPAMBW1_EL12, x0
+msr MPAMBW0_EL1, x0
+msr MPAMBWCAP_EL2, x0
+msr MPAMBWSM_EL1, x0
+
+mrs x0, MPAMBWIDR_EL1
+mrs x0, MPAMBW3_EL3
+mrs x0, MPAMBW2_EL2
+mrs x0, MPAMBW1_EL1
+mrs x0, MPAMBW1_EL12
+mrs x0, MPAMBW0_EL1
+mrs x0, MPAMBWCAP_EL2
+mrs x0, MPAMBWSM_EL1
+
+//CHECK: msr MPAMBW3_EL3, x0 // encoding: [0x80,0xa5,0x1e,0xd5]
+//CHECK: msr MPAMBW2_EL2, x0 // encoding: [0x80,0xa5,0x1c,0xd5]
+//CHECK: msr MPAMBW1_EL1, x0 // encoding: [0x80,0xa5,0x18,0xd5]
+//CHECK: msr MPAMBW1_EL12, x0 // encoding: [0x80,0xa5,0x1d,0xd5]
+//CHECK: msr MPAMBW0_EL1, x0 // encoding: [0xa0,0xa5,0x18,0xd5]
+//CHECK: msr MPAMBWCAP_EL2, x0 // encoding: [0xc0,0xa5,0x1c,0xd5]
+//CHECK: msr MPAMBWSM_EL1, x0 // encoding: [0xe0,0xa5,0x18,0xd5]
+
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-RO: msr MPAMBWIDR_EL1, x0
+//CHECK-RO: ^
+
+//CHECK: mrs x0, MPAMBWIDR_EL1 // encoding: [0xa0,0xa4,0x38,0xd5]
+//CHECK: mrs x0, MPAMBW3_EL3 // encoding: [0x80,0xa5,0x3e,0xd5]
+//CHECK: mrs x0, MPAMBW2_EL2 // encoding: [0x80,0xa5,0x3c,0xd5]
+//CHECK: mrs x0, MPAMBW1_EL1 // encoding: [0x80,0xa5,0x38,0xd5]
+//CHECK: mrs x0, MPAMBW1_EL12 // encoding: [0x80,0xa5,0x3d,0xd5]
+//CHECK: mrs x0, MPAMBW0_EL1 // encoding: [0xa0,0xa5,0x38,0xd5]
+//CHECK: mrs x0, MPAMBWCAP_EL2 // encoding: [0xc0,0xa5,0x3c,0xd5]
+//CHECK: mrs x0, MPAMBWSM_EL1 // encoding: [0xe0,0xa5,0x38,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt
new file mode 100644
index 00000000000000..b9ff0a4d209b2f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s
+
+#------------------------------------------------------------------------------
+# Armv9.6-A FEAT_MPAM Extensions
+#------------------------------------------------------------------------------
+
+[0x80,0xa5,0x1e,0xd5]
+# CHECK: msr MPAMBW3_EL3, x0
+
+[0x80,0xa5,0x1c,0xd5]
+# CHECK: msr MPAMBW2_EL2, x0
+
+[0x80,0xa5,0x18,0xd5]
+# CHECK: msr MPAMBW1_EL1, x0
+
+[0x80,0xa5,0x1d,0xd5]
+# CHECK: msr MPAMBW1_EL12, x0
+
+[0xa0,0xa5,0x18,0xd5]
+# CHECK: msr MPAMBW0_EL1, x0
+
+[0xc0,0xa5,0x1c,0xd5]
+# CHECK: msr MPAMBWCAP_EL2, x0
+
+[0xe0,0xa5,0x18,0xd5]
+# CHECK: msr MPAMBWSM_EL1, x0
+
+[0xa0,0xa4,0x38,0xd5]
+# CHECK: mrs x0, MPAMBWIDR_EL1
+
+[0x80,0xa5,0x3e,0xd5]
+# CHECK: mrs x0, MPAMBW3_EL3
+
+[0x80,0xa5,0x3c,0xd5]
+# CHECK: mrs x0, MPAMBW2_EL2
+
+[0x80,0xa5,0x38,0xd5]
+# CHECK: mrs x0, MPAMBW1_EL1
+
+[0x80,0xa5,0x3d,0xd5]
+# CHECK: mrs x0, MPAMBW1_EL12
+
+[0xa0,0xa5,0x38,0xd5]
+# CHECK: mrs x0, MPAMBW0_EL1
+
+[0xc0,0xa5,0x3c,0xd5]
+# CHECK: mrs x0, MPAMBWCAP_EL2
+
+[0xe0,0xa5,0x38,0xd5]
+# CHECK: mrs x0, MPAMBWSM_EL1
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