[clang] [llvm] [RISCV] Add Smrnmi extension (PR #111668)

[Craig Topper via llvm-commits]

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@@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero
 csrrs t2, 0xB1F, zero
 
 
+######################################
+# Machine Counter Setup
----------------
topperc wrote:

Section title is incorrect.

The registers are already tested in rv32-machine-csr-names.s but they should be in this file. That was a mistake.

https://github.com/llvm/llvm-project/pull/111668