[llvm] [CodeGen] [AMDGPU] Attempt DAGCombine for fmul with select to ldexp (PR #111109)

[Matt Arsenault via llvm-commits]

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@@ -14510,25 +14506,36 @@ SDValue SITargetLowering::performFMulCombine(SDNode *N,
 
       if (TrueNode->isNegative() != FalseNode->isNegative())
         return SDValue();
-      bool isNeg = TrueNode->isNegative();
+      LHS = TrueNode->isNegative() ? DAG.getNode(ISD::FNEG, SL, VT, LHS) : LHS;
 
-      unsigned ExtOp;
+      // fmul x, (select y, 2.0, 1.0)   -> ldexp(  x, zext(i1 y) )
+      // fmul x, (select y, -2.0, -1.0) -> ldexp( (fneg x), zext(i1 y) )
+      // fmul x, (select y, 0.5, 1.0)   -> ldexp(  x, sext(i1 y) )
+      // fmul x, (select y, -0.5, -1.0) -> ldexp( (fneg x), sext(i1 y) )
       if (FalseNode->isExactlyValue(1.0) || FalseNode->isExactlyValue(-1.0)) {
-        if (TrueNode->isExactlyValue(2.0) || TrueNode->isExactlyValue(-2.0))
-          ExtOp = ISD::ZERO_EXTEND;
-        else if (TrueNode->isExactlyValue(0.5) ||
-                 TrueNode->isExactlyValue(-0.5))
-          ExtOp = ISD::SIGN_EXTEND;
-        else
-          return SDValue();
+        if (TrueNode->isExactlyValue(2.0) || TrueNode->isExactlyValue(-2.0)) {
+          SDValue ZExtNode =
+              DAG.getNode(ISD::ZERO_EXTEND, SL, i32VT, RHS.getOperand(0));
+          return DAG.getNode(ISD::FLDEXP, SL, VT, LHS, ZExtNode);
+        } else if (TrueNode->isExactlyValue(0.5) ||
+                   TrueNode->isExactlyValue(-0.5)) {
+          SDValue SExtNode =
+              DAG.getNode(ISD::SIGN_EXTEND, SL, i32VT, RHS.getOperand(0));
+          return DAG.getNode(ISD::FLDEXP, SL, VT, LHS, SExtNode);
+        }
+      }
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arsenm wrote:

You don't need the special case for the extensions up here. We select the extensions into a select anyway 

https://github.com/llvm/llvm-project/pull/111109