[llvm] [X86][ABIVerifier] Verify floating point ABI correctness on 64-bit target (PR #111690)

[Phoebe Wang via llvm-commits]

================
@@ -2086,6 +2088,27 @@ void Verifier::checkUnsignedBaseTenFuncAttr(AttributeList Attrs, StringRef Attr,
   }
 }
 
+void Verifier::verifyX86ABI(FunctionType *FT, AttributeList Attrs,
+                            const Value *V, unsigned MaxParameterWidth) {
+  if (!Attrs.hasFnAttr("target-features"))
+    return;
+
+  StringRef TF = Attrs.getFnAttr("target-features").getValueAsString();
+  // Check SSE feature.
+  Check(!TT.isArch64Bit() || !TF.contains("-sse,") ||
+        !FT->getReturnType()->isFloatTy(),
+        "SSE register return with SSE disabled", V);
+  // Check SSE2 feature.
+  Check(!TT.isArch64Bit() || !TF.contains("-sse2") ||
+        (!FT->getReturnType()->isDoubleTy() &&
+         !FT->getReturnType()->is16bitFPTy()),
+        "SSE2 register return with SSE2 disabled", V);
+  // Check EVEX512 feature.
+  if (MaxParameterWidth >= 512)
+    Check(!TF.contains("+avx512f") || !TF.contains("-evex512"),
+          "512-bit vector arguments require 'evex512' for AVX512", V);
+}
----------------
phoebewang wrote:

https://github.com/llvm/llvm-project/issues/111406 is a good illustration to this question. Arbitrarily generating something is unexpected here.

https://github.com/llvm/llvm-project/pull/111690