[llvm] [AMDGPU] Include WWM register spill into BB Prolog (PR #111496)

[via llvm-commits]

alex-t wrote:

Adding any VGPR reload to the prologue will take us back to the SplitKit assert issue.
Since WWM VGPR reload creates a new live interval in the VGPR it defines, we end up at the same point where we started.

SplitKit may decide to split some Vreg across the reloaded VGPR in this basic block and the split point, according to the isBasicBlockPrologue will be evaluated after the v15 definition (i.e. after the live interval starts). So, we again will hit an assert for interference.

https://github.com/llvm/llvm-project/pull/111496