[llvm] [AArch64] Disable consecutive store merging when Neon is unavailable (PR #111519)

[Benjamin Maxwell via llvm-commits]

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@@ -27924,6 +27924,24 @@ bool AArch64TargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
   return OptSize && !VT.isVector();
 }
 
+bool AArch64TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
+                                             const MachineFunction &MF) const {
+  // Avoid merging stores into fixed-length vectors when Neon is unavailable.
+  // In future, we could allow this when SVE is available, but currently,
+  // the SVE lowerings for BUILD_VECTOR are limited to a few specific cases (and
+  // the general lowering may introduce stack spills/reloads).
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MacDue wrote:

> The part that isn't entirely clear to me yet is for which cases we'd want to enable this merging when we do have optimal SVE codegen.

I'm not sure either, but the original commit (from way back when) for the DAG combine only handled stores of constants and loads and noted it's generally not profitable (see: https://github.com/llvm/llvm-project/commit/7cbc12a41d72bf106e3075878b4f1f6047085e87). The way it's merging stores of extracts here is a little odd and _maybe_ unintentional? It'd make more sense to do the merge if it was storing lanes from the same vector, which is not the case here.

https://github.com/llvm/llvm-project/pull/111519