[llvm] [RISCV][VCIX] Add a tied constraint between rd and rs3 in sf.v.xvv and sf.v.xvw instructions (PR #111630)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 8 22:24:00 PDT 2024

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topperc wrote:

FYI @michalt

https://github.com/llvm/llvm-project/pull/111630

Previous message: [llvm] [RISCV][VCIX] Add a tied constraint between rd and rs3 in sf.v.xvv and sf.v.xvw instructions (PR #111630)
Next message: [llvm] [CodeGen][MRI] Add allocation mask for register classes (PR #86007)
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