[llvm] 1a19313 - [RISC-V][HWASAN] Fix incorrect comments (#103728)
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Tue Oct 8 16:00:48 PDT 2024
Author: Samuel Holland
Date: 2024-10-08T16:00:45-07:00
New Revision: 1a193137e3125c3abb107dd4e526163e0851253a
URL: https://github.com/llvm/llvm-project/commit/1a193137e3125c3abb107dd4e526163e0851253a
DIFF: https://github.com/llvm/llvm-project/commit/1a193137e3125c3abb107dd4e526163e0851253a.diff
LOG: [RISC-V][HWASAN] Fix incorrect comments (#103728)
These comments were confusing because they do not match the code.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 69ab49de1dacad..52d0a70d335e97 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -679,12 +679,12 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
OutStreamer->emitInstruction(
MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
MCSTI);
- // Extract tag from X5 and compare it with loaded tag from shadow
+ // Extract tag from pointer and compare it with loaded tag from shadow
OutStreamer->emitInstruction(
MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56),
MCSTI);
MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
- // X7 contains tag from memory, while X6 contains tag from the pointer
+ // X7 contains tag from the pointer, while X6 contains tag from memory
OutStreamer->emitInstruction(
MCInstBuilder(RISCV::BNE)
.addReg(RISCV::X7)
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