[clang] [llvm] [BPF] Add load-acquire and store-release instructions under -mcpu=v4 (PR #108636)

[via llvm-commits]

yonghong-song wrote:

For
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About whether we should sign-extend for 8- and 16-bit load-acquires (brought up by Yonghong):

All ARM64 insns that match acquiring_load<atomic_load[_az]_{8,16}> seem to zero-extend the value before writing it to register, like, LDAPRH:

    Load-Acquire RCpc Register Halfword derives an address from a base register value, loads a halfword from the derived address in memory, zero-extends it and writes it to a register.

So right now I'm keeping our LDBACQ32 and LDHACQ32 to zero-extend. I'll take a look at other archs later.
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I think you need to implement kernel part to utilize the newly-introduced bpf insns. Then we can see whether jit'ed code works as expected or not.

https://github.com/llvm/llvm-project/pull/108636