[llvm] [CodeGen] Correctly handle non-standard cases in RemoveLoadsIntoFakeUses (PR #111551)

[Stephen Tozer via llvm-commits]

================
@@ -109,31 +112,38 @@ bool RemoveLoadsIntoFakeUses::runOnMachineFunction(MachineFunction &MF) {
       // reload of a spilled register.
       if (MI.getRestoreSize(TII)) {
         Register Reg = MI.getOperand(0).getReg();
-        assert(Reg.isPhysical() && "VReg seen in function with NoVRegs set?");
         // Don't delete live physreg defs, or any reserved register defs.
         if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
           continue;
-        // There should be an exact match between the loaded register and the
-        // FAKE_USE use. If not, this is a load that is unused by anything? It
-        // should probably be deleted, but that's outside of this pass' scope.
-        if (RegFakeUses.contains(Reg)) {
+        // There should typically be an exact match between the loaded register
+        // and the FAKE_USE, but sometimes regalloc will choose to load a larger
+        // value than is needed. Therefore, as long as the load isn't used by
----------------
SLTozer wrote:

I can post a full file if you want, but to summarize with snippets:
Pre-regalloc we have:
```
bb.5.for.end16:
  %2:gr32 = COPY killed %19:gr32
  FAKE_USE killed %2:gr32
  ...
```
After some merging, including %2 merging with %19, we get:
```
544B	bb.5.for.end16:
576B	  FAKE_USE %20.sub_32bit:gr64_with_sub_8bit
```
Then, after the following update:
```
selectOrSplit GR64_with_sub_8bit:%20 [120r,432B:0)[472r,544B:1)[544B,576r:2) 0 at 120r 1 at 472r 2 at 544B-phi  weight:5.118239e-02 w=5.118239e-02
RS_Spill Cascade 0
Inline spilling GR64_with_sub_8bit:%20 [120r,432B:0)[472r,544B:1)[544B,576r:2) 0 at 120r 1 at 472r 2 at 544B-phi  weight:5.118239e-02
>From original %14
	cannot remat for 576e	FAKE_USE %20.sub_32bit:gr64_with_sub_8bit
Merged spilled regs: SS#0 [120r,432B:0)[472r,576r:0) 0 at x  weight:0.000000e+00
spillAroundUses %20
	merged orig valno 1: SS#0 [112B,432B:0)[472r,576r:0) 0 at x  weight:0.000000e+00
Checking redundant spills for 1 at 112B in %21 [96r,112B:0)[112B,120r:1)[592r,672B:2) 0 at 96r 1 at 112B-phi 2 at 592r  weight:1.348007e-01
Merged to stack int: SS#0 [112B,432B:0)[472r,576r:0) 0 at x  weight:0.000000e+00
Checking redundant spills for 0 at 120r in %20 [120r,432B:0)[472r,544B:1)[544B,576r:2) 0 at 120r 1 at 472r 2 at 544B-phi  weight:5.118239e-02
	hoisted: 112B	MOV64mr %stack.0, 1, $noreg, 0, $noreg, %21:gr64_with_sub_8bit :: (store (s64) into %stack.0)
	folded:   472r	MOV64mi32 %stack.0, 1, $noreg, 0, $noreg, 0 :: (store (s64) into %stack.0)
	reload:   552r	%23:gr64_with_sub_8bit = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0)
	rewrite: 576r	FAKE_USE killed %23.sub_32bit:gr64_with_sub_8bit
```
We end up with:
```
544B	bb.5.for.end16:
552B	  %23:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0)
576B	  FAKE_USE %23.sub_32bit:gr64
```
Which becomes:
```
bb.5.for.end16:
  renamable $rax = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0)
  FAKE_USE renamable $eax, implicit killed $rax
```
Where `$rax` is entirely unused outside of the `FAKE_USE` of `$eax`.

https://github.com/llvm/llvm-project/pull/111551