[llvm] [AMDGPU] Constrain use LiveMask by the operand's LaneMask for RP calculation. (PR #111452)
Jeffrey Byrnes via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 8 08:23:55 PDT 2024
================
@@ -259,33 +259,40 @@ static void
collectVirtualRegUses(SmallVectorImpl<RegisterMaskPair> &RegMaskPairs,
const MachineInstr &MI, const LiveIntervals &LIS,
const MachineRegisterInfo &MRI) {
- SlotIndex InstrSI;
+
+ auto &TRI = *MRI.getTargetRegisterInfo();
for (const auto &MO : MI.operands()) {
if (!MO.isReg() || !MO.getReg().isVirtual())
continue;
if (!MO.isUse() || !MO.readsReg())
continue;
Register Reg = MO.getReg();
- if (llvm::any_of(RegMaskPairs, [Reg](const RegisterMaskPair &RM) {
- return RM.RegUnit == Reg;
- }))
- continue;
+ auto I = llvm::find_if(RegMaskPairs, [Reg](const RegisterMaskPair &RM) {
+ return RM.RegUnit == Reg;
+ });
+
+ auto &P = I == RegMaskPairs.end()
+ ? RegMaskPairs.emplace_back(Reg, LaneBitmask::getNone())
+ : *I;
- LaneBitmask UseMask;
- auto &LI = LIS.getInterval(Reg);
+ P.LaneMask |= MO.getSubReg() ? TRI.getSubRegIndexLaneMask(MO.getSubReg())
+ : MRI.getMaxLaneMaskForVReg(Reg);
----------------
jrbyrnes wrote:
`MRI.getMaxLaneMaskForVReg` uses the `TRC` for width-aware `LaneMask`s whereas `TRI.getSubRegIndexLaneMask just returns `~0u`
https://github.com/llvm/llvm-project/pull/111452
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