[llvm] [CodeGen] [AMDGPU] Adds pre-commit test for fmul-select combine (PR #111107)
Vikash Gupta via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 8 03:30:57 PDT 2024
https://github.com/vg0204 updated https://github.com/llvm/llvm-project/pull/111107
>From 277c51ac5f06c8783fb00f1c5a7c9c278537f77d Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Fri, 4 Oct 2024 06:53:37 +0000
Subject: [PATCH 1/3] [CodeGen] [AMDGPU] Adds pre-commit test for fmul-select
combine
This adds the f32/f64 test cases for below pattern :
fmul x, select(y, 2.0, 1.0)
fmul x, select(y, 0.5, 1.0)
It acts as pre-commit tests for dagCombine above pattern into cheaper
ldexp in f64 case.
---
llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll | 342 +++++++++++++++++++
1 file changed, 342 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll
diff --git a/llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll
new file mode 100644
index 00000000000000..c20cf332422fef
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll
@@ -0,0 +1,342 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+;RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+;RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs | FileCheck -check-prefix=GFX1030 %s
+;RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefix=GFX1100 %s
+
+define float @fmul_select_f32_test1(float %x, i1 %bool) {
+; GFX9-LABEL: fmul_select_f32_test1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f32_test1:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX1030-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f32_test1:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX1100-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo
+; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %1 = select i1 %bool, float 2.000000e+00, float 1.000000e+00
+ %ldexp = fmul float %x, %1
+ ret float %ldexp
+}
+
+define float @fmul_select_f32_test2(float %x, i1 %bool) {
+; GFX9-LABEL: fmul_select_f32_test2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f32_test2:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX1030-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f32_test2:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX1100-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo
+; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %1 = select i1 %bool, float 0.500000e+00, float 1.000000e+00
+ %ldexp = fmul float %x, %1
+ ret float %ldexp
+}
+
+define <2 x float> @fmul_select_v2f32_test1(<2 x float> %x, <2 x i1> %bool) {
+; GFX9-LABEL: fmul_select_v2f32_test1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_v2f32_test1:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX1030-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_v2f32_test1:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX1100-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo
+; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_and_b32 v3, 1, v3
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX1100-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo
+; GFX1100-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %1 = select <2 x i1> %bool, <2 x float> <float 2.000000e+00, float 2.000000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
+ %ldexp = fmul <2 x float> %x, %1
+ ret <2 x float> %ldexp
+}
+
+define <2 x float> @fmul_select_v2f32_test2(<2 x float> %x, <2 x i1> %bool) {
+; GFX9-LABEL: fmul_select_v2f32_test2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_v2f32_test2:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX1030-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_v2f32_test2:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX1100-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo
+; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_and_b32 v3, 1, v3
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX1100-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo
+; GFX1100-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %1 = select <2 x i1> %bool, <2 x float> <float 0.500000e+00, float 0.500000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
+ %ldexp = fmul <2 x float> %x, %1
+ ret <2 x float> %ldexp
+}
+
+define double @fmul_select_f64_test1(double %x, i1 %bool) {
+; GFX9-LABEL: fmul_select_f64_test1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x3ff00000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, 2.0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test1:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_and_b32_e32 v3, 1, v2
+; GFX1030-NEXT: v_mov_b32_e32 v2, 0
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX1030-NEXT: v_cndmask_b32_e64 v3, 0x3ff00000, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test1:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 1, v2
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX1100-NEXT: v_cndmask_b32_e64 v3, 0x3ff00000, 2.0, vcc_lo
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %1 = select i1 %bool, double 2.000000e+00, double 1.000000e+00
+ %ldexp = fmul double %x, %1
+ ret double %ldexp
+}
+
+define double @fmul_select_f64_test2(double %x, i1 %bool) {
+; GFX9-LABEL: fmul_select_f64_test2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x3ff00000
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x3fe00000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test2:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_and_b32_e32 v3, 1, v2
+; GFX1030-NEXT: v_mov_b32_e32 v4, 0x3fe00000
+; GFX1030-NEXT: v_mov_b32_e32 v2, 0
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX1030-NEXT: v_cndmask_b32_e32 v3, 0x3ff00000, v4, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test2:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_dual_mov_b32 v4, 0x3fe00000 :: v_dual_and_b32 v3, 1, v2
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX1100-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, 0x3ff00000, v4
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %1 = select i1 %bool, double 0.500000e+00, double 1.000000e+00
+ %ldexp = fmul double %x, %1
+ ret double %ldexp
+}
+
+define <2 x double> @fmul_select_v2f64_test1(<2 x double> %x, <2 x i1> %bool) {
+; GFX9-LABEL: fmul_select_v2f64_test1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v6, 1, v4
+; GFX9-NEXT: v_and_b32_e32 v7, 1, v5
+; GFX9-NEXT: v_mov_b32_e32 v8, 0x3ff00000
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, 2.0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v5, v4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[5:6]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, 2.0, vcc
+; GFX9-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_v2f64_test1:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_and_b32_e32 v6, 1, v4
+; GFX1030-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX1030-NEXT: v_mov_b32_e32 v4, 0
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX1030-NEXT: v_mov_b32_e32 v6, v4
+; GFX1030-NEXT: v_cndmask_b32_e64 v7, 0x3ff00000, 2.0, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[6:7]
+; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0x3ff00000, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_v2f64_test1:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_and_b32_e32 v6, 1, v4
+; GFX1100-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v5, 1, v5
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX1100-NEXT: v_mov_b32_e32 v6, v4
+; GFX1100-NEXT: v_cndmask_b32_e64 v7, 0x3ff00000, 2.0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[6:7]
+; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0x3ff00000, 2.0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %1 = select <2 x i1> %bool, <2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %1
+ ret <2 x double> %ldexp
+}
+
+define <2 x double> @fmul_select_v2f64_test2(<2 x double> %x, <2 x i1> %bool) {
+; GFX9-LABEL: fmul_select_v2f64_test2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v6, 1, v4
+; GFX9-NEXT: v_and_b32_e32 v7, 1, v5
+; GFX9-NEXT: v_mov_b32_e32 v8, 0x3ff00000
+; GFX9-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc
+; GFX9-NEXT: v_mov_b32_e32 v5, v4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[5:6]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
+; GFX9-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_v2f64_test2:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_and_b32_e32 v6, 1, v4
+; GFX1030-NEXT: v_mov_b32_e32 v8, 0x3fe00000
+; GFX1030-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX1030-NEXT: v_mov_b32_e32 v4, 0
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX1030-NEXT: v_mov_b32_e32 v6, v4
+; GFX1030-NEXT: v_cndmask_b32_e32 v7, 0x3ff00000, v8, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[6:7]
+; GFX1030-NEXT: v_cndmask_b32_e32 v5, 0x3ff00000, v8, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_v2f64_test2:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_and_b32_e32 v6, 1, v4
+; GFX1100-NEXT: v_dual_mov_b32 v8, 0x3fe00000 :: v_dual_and_b32 v5, 1, v5
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX1100-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v7, 0x3ff00000, v8
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX1100-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_cndmask_b32 v5, 0x3ff00000, v8
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[6:7]
+; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %1 = select <2 x i1> %bool, <2 x double> <double 0.500000e+00, double 0.500000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %1
+ ret <2 x double> %ldexp
+}
>From 258b672b2db20b70878fab6f4f361cef1350c0ed Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Mon, 7 Oct 2024 11:02:14 +0000
Subject: [PATCH 2/3] Added test cases for f16, wrong constants, & negative
constants.
---
llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll | 342 --------
.../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 781 ++++++++++++++++++
2 files changed, 781 insertions(+), 342 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
diff --git a/llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll
deleted file mode 100644
index c20cf332422fef..00000000000000
--- a/llvm/test/CodeGen/AMDGPU/combine-fmul-sel.ll
+++ /dev/null
@@ -1,342 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-;RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
-;RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs | FileCheck -check-prefix=GFX1030 %s
-;RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefix=GFX1100 %s
-
-define float @fmul_select_f32_test1(float %x, i1 %bool) {
-; GFX9-LABEL: fmul_select_f32_test1:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc
-; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-LABEL: fmul_select_f32_test1:
-; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX1030-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo
-; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX1030-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: fmul_select_f32_test1:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo
-; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
- %1 = select i1 %bool, float 2.000000e+00, float 1.000000e+00
- %ldexp = fmul float %x, %1
- ret float %ldexp
-}
-
-define float @fmul_select_f32_test2(float %x, i1 %bool) {
-; GFX9-LABEL: fmul_select_f32_test2:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc
-; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-LABEL: fmul_select_f32_test2:
-; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX1030-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo
-; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX1030-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: fmul_select_f32_test2:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo
-; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
- %1 = select i1 %bool, float 0.500000e+00, float 1.000000e+00
- %ldexp = fmul float %x, %1
- ret float %ldexp
-}
-
-define <2 x float> @fmul_select_v2f32_test1(<2 x float> %x, <2 x i1> %bool) {
-; GFX9-LABEL: fmul_select_v2f32_test1:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc
-; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-LABEL: fmul_select_v2f32_test1:
-; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX1030-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX1030-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX1030-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo
-; GFX1030-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX1030-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: fmul_select_v2f32_test1:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo
-; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_and_b32 v3, 1, v3
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX1100-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo
-; GFX1100-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
- %1 = select <2 x i1> %bool, <2 x float> <float 2.000000e+00, float 2.000000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
- %ldexp = fmul <2 x float> %x, %1
- ret <2 x float> %ldexp
-}
-
-define <2 x float> @fmul_select_v2f32_test2(<2 x float> %x, <2 x i1> %bool) {
-; GFX9-LABEL: fmul_select_v2f32_test2:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc
-; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-LABEL: fmul_select_v2f32_test2:
-; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX1030-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX1030-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX1030-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo
-; GFX1030-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX1030-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: fmul_select_v2f32_test2:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo
-; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_and_b32 v3, 1, v3
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX1100-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo
-; GFX1100-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
- %1 = select <2 x i1> %bool, <2 x float> <float 0.500000e+00, float 0.500000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
- %ldexp = fmul <2 x float> %x, %1
- ret <2 x float> %ldexp
-}
-
-define double @fmul_select_f64_test1(double %x, i1 %bool) {
-; GFX9-LABEL: fmul_select_f64_test1:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x3ff00000
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, 2.0, vcc
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-LABEL: fmul_select_f64_test1:
-; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-NEXT: v_and_b32_e32 v3, 1, v2
-; GFX1030-NEXT: v_mov_b32_e32 v2, 0
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX1030-NEXT: v_cndmask_b32_e64 v3, 0x3ff00000, 2.0, vcc_lo
-; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
-; GFX1030-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: fmul_select_f64_test1:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX1100-NEXT: v_cndmask_b32_e64 v3, 0x3ff00000, 2.0, vcc_lo
-; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
- %1 = select i1 %bool, double 2.000000e+00, double 1.000000e+00
- %ldexp = fmul double %x, %1
- ret double %ldexp
-}
-
-define double @fmul_select_f64_test2(double %x, i1 %bool) {
-; GFX9-LABEL: fmul_select_f64_test2:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x3ff00000
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x3fe00000
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-LABEL: fmul_select_f64_test2:
-; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-NEXT: v_and_b32_e32 v3, 1, v2
-; GFX1030-NEXT: v_mov_b32_e32 v4, 0x3fe00000
-; GFX1030-NEXT: v_mov_b32_e32 v2, 0
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX1030-NEXT: v_cndmask_b32_e32 v3, 0x3ff00000, v4, vcc_lo
-; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
-; GFX1030-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: fmul_select_f64_test2:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_dual_mov_b32 v4, 0x3fe00000 :: v_dual_and_b32 v3, 1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX1100-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, 0x3ff00000, v4
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
- %1 = select i1 %bool, double 0.500000e+00, double 1.000000e+00
- %ldexp = fmul double %x, %1
- ret double %ldexp
-}
-
-define <2 x double> @fmul_select_v2f64_test1(<2 x double> %x, <2 x i1> %bool) {
-; GFX9-LABEL: fmul_select_v2f64_test1:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v4
-; GFX9-NEXT: v_and_b32_e32 v7, 1, v5
-; GFX9-NEXT: v_mov_b32_e32 v8, 0x3ff00000
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, 2.0, vcc
-; GFX9-NEXT: v_mov_b32_e32 v5, v4
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
-; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[5:6]
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, 2.0, vcc
-; GFX9-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-LABEL: fmul_select_v2f64_test1:
-; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-NEXT: v_and_b32_e32 v6, 1, v4
-; GFX1030-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX1030-NEXT: v_mov_b32_e32 v4, 0
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX1030-NEXT: v_mov_b32_e32 v6, v4
-; GFX1030-NEXT: v_cndmask_b32_e64 v7, 0x3ff00000, 2.0, vcc_lo
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
-; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[6:7]
-; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0x3ff00000, 2.0, vcc_lo
-; GFX1030-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
-; GFX1030-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: fmul_select_v2f64_test1:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_and_b32_e32 v6, 1, v4
-; GFX1100-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v5, 1, v5
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX1100-NEXT: v_mov_b32_e32 v6, v4
-; GFX1100-NEXT: v_cndmask_b32_e64 v7, 0x3ff00000, 2.0, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
-; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[6:7]
-; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0x3ff00000, 2.0, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
- %1 = select <2 x i1> %bool, <2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
- %ldexp = fmul <2 x double> %x, %1
- ret <2 x double> %ldexp
-}
-
-define <2 x double> @fmul_select_v2f64_test2(<2 x double> %x, <2 x i1> %bool) {
-; GFX9-LABEL: fmul_select_v2f64_test2:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v4
-; GFX9-NEXT: v_and_b32_e32 v7, 1, v5
-; GFX9-NEXT: v_mov_b32_e32 v8, 0x3ff00000
-; GFX9-NEXT: v_mov_b32_e32 v9, 0x3fe00000
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc
-; GFX9-NEXT: v_mov_b32_e32 v5, v4
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
-; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[5:6]
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc
-; GFX9-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1030-LABEL: fmul_select_v2f64_test2:
-; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1030-NEXT: v_and_b32_e32 v6, 1, v4
-; GFX1030-NEXT: v_mov_b32_e32 v8, 0x3fe00000
-; GFX1030-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX1030-NEXT: v_mov_b32_e32 v4, 0
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX1030-NEXT: v_mov_b32_e32 v6, v4
-; GFX1030-NEXT: v_cndmask_b32_e32 v7, 0x3ff00000, v8, vcc_lo
-; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
-; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[6:7]
-; GFX1030-NEXT: v_cndmask_b32_e32 v5, 0x3ff00000, v8, vcc_lo
-; GFX1030-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
-; GFX1030-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: fmul_select_v2f64_test2:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_and_b32_e32 v6, 1, v4
-; GFX1100-NEXT: v_dual_mov_b32 v8, 0x3fe00000 :: v_dual_and_b32 v5, 1, v5
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX1100-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v7, 0x3ff00000, v8
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
-; GFX1100-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_cndmask_b32 v5, 0x3ff00000, v8
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[6:7]
-; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[4:5]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
- %1 = select <2 x i1> %bool, <2 x double> <double 0.500000e+00, double 0.500000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
- %ldexp = fmul <2 x double> %x, %1
- ret <2 x double> %ldexp
-}
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
new file mode 100644
index 00000000000000..62ba95b9f8a0c0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -0,0 +1,781 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX1030 %s
+;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX1100 %s
+
+define float @fmul_select_f32_test1(float %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f32_test1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f32_test1:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f32_test1:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1100-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, float 2.000000e+00, float 1.000000e+00
+ %ldexp = fmul float %x, %1
+ ret float %ldexp
+}
+
+define float @fmul_select_f32_test2(float %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f32_test2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f32_test2:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f32_test2:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1100-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, float 0.500000e+00, float 1.000000e+00
+ %ldexp = fmul float %x, %1
+ ret float %ldexp
+}
+
+define <2 x float> @fmul_select_f32_test3(<2 x float> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) {
+; GFX9-LABEL: fmul_select_f32_test3:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f32_test3:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX1030-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f32_test3:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX1100-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5
+; GFX1100-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
+ %1 = select <2 x i1> %bool, <2 x float> <float 2.000000e+00, float 2.000000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
+ %ldexp = fmul <2 x float> %x, %1
+ ret <2 x float> %ldexp
+}
+
+define <2 x float> @fmul_select_f32_test4(<2 x float> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) {
+; GFX9-LABEL: fmul_select_f32_test4:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f32_test4:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX1030-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f32_test4:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX1100-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5
+; GFX1100-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
+ %1 = select <2 x i1> %bool, <2 x float> <float 0.500000e+00, float 0.500000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
+ %ldexp = fmul <2 x float> %x, %1
+ ret <2 x float> %ldexp
+}
+
+define float @fmul_select_f32_test5(float %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f32_test5:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f32_test5:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f32_test5:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1100-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, float -2.000000e+00, float -1.000000e+00
+ %ldexp = fmul float %x, %1
+ ret float %ldexp
+}
+
+define float @fmul_select_f32_test6(float %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f32_test6:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x41000000
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x40400000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f32_test6:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v3, 0x40400000
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x41000000, v3, vcc_lo
+; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f32_test6:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_mov_b32_e32 v3, 0x40400000
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x41000000, v3, vcc_lo
+; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, float 3.000000e+00, float 8.000000e+00
+ %ldexp = fmul float %x, %1
+ ret float %ldexp
+}
+
+define double @fmul_select_f64_test1(double %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x3ff00000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, 2.0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test1:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1030-NEXT: v_mov_b32_e32 v4, 0
+; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0x3ff00000, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test1:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1100-NEXT: v_mov_b32_e32 v4, 0
+; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0x3ff00000, 2.0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, double 2.000000e+00, double 1.000000e+00
+ %ldexp = fmul double %x, %1
+ ret double %ldexp
+}
+
+define double @fmul_select_f64_test2(double %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x3ff00000
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x3fe00000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test2:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v5, 0x3fe00000
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1030-NEXT: v_mov_b32_e32 v4, 0
+; GFX1030-NEXT: v_cndmask_b32_e32 v5, 0x3ff00000, v5, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test2:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_dual_mov_b32 v5, 0x3fe00000 :: v_dual_mov_b32 v4, 0
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e32 v5, 0x3ff00000, v5, vcc_lo
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, double 0.500000e+00, double 1.000000e+00
+ %ldexp = fmul double %x, %1
+ ret double %ldexp
+}
+
+define <2 x double> @fmul_select_f64_test3(<2 x double> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test3:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v11, 0x3ff00000
+; GFX9-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v11, 2.0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[9:10]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v11, 2.0, vcc
+; GFX9-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test3:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
+; GFX1030-NEXT: v_mov_b32_e32 v8, 0
+; GFX1030-NEXT: v_cndmask_b32_e64 v11, 0x3ff00000, 2.0, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
+; GFX1030-NEXT: v_mov_b32_e32 v10, v8
+; GFX1030-NEXT: v_cndmask_b32_e64 v9, 0x3ff00000, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[10:11]
+; GFX1030-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test3:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
+; GFX1100-NEXT: v_mov_b32_e32 v8, 0
+; GFX1100-NEXT: v_cndmask_b32_e64 v11, 0x3ff00000, 2.0, vcc_lo
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_mov_b32_e32 v10, v8
+; GFX1100-NEXT: v_cndmask_b32_e64 v9, 0x3ff00000, 2.0, vcc_lo
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[10:11]
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
+ %1 = select <2 x i1> %bool, <2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %1
+ ret <2 x double> %ldexp
+}
+
+define <2 x double> @fmul_select_f64_test4(<2 x double> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test4:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v11, 0x3ff00000
+; GFX9-NEXT: v_mov_b32_e32 v12, 0x3fe00000
+; GFX9-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[9:10]
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc
+; GFX9-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test4:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
+; GFX1030-NEXT: v_mov_b32_e32 v8, 0
+; GFX1030-NEXT: v_cndmask_b32_e32 v11, 0x3ff00000, v9, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
+; GFX1030-NEXT: v_mov_b32_e32 v10, v8
+; GFX1030-NEXT: v_cndmask_b32_e32 v9, 0x3ff00000, v9, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[10:11]
+; GFX1030-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test4:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_dual_mov_b32 v9, 0x3fe00000 :: v_dual_mov_b32 v8, 0
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_dual_mov_b32 v10, v8 :: v_dual_cndmask_b32 v11, 0x3ff00000, v9
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[10:11]
+; GFX1100-NEXT: v_cndmask_b32_e32 v9, 0x3ff00000, v9, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
+ %1 = select <2 x i1> %bool, <2 x double> <double 0.500000e+00, double 0.500000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %1
+ ret <2 x double> %ldexp
+}
+
+define double @fmul_select_f64_test5(double %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test5:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xbff00000
+; GFX9-NEXT: v_mov_b32_e32 v5, 0xbfe00000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test5:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v5, 0xbfe00000
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1030-NEXT: v_mov_b32_e32 v4, 0
+; GFX1030-NEXT: v_cndmask_b32_e32 v5, 0xbff00000, v5, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test5:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_dual_mov_b32 v5, 0xbfe00000 :: v_dual_mov_b32 v4, 0
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e32 v5, 0xbff00000, v5, vcc_lo
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, double -0.500000e+00, double -1.000000e+00
+ %ldexp = fmul double %x, %1
+ ret double %ldexp
+}
+
+define double @fmul_select_f64_test6(double %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test6:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xbff00000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, -2.0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test6:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1030-NEXT: v_mov_b32_e32 v4, 0
+; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, -2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test6:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1100-NEXT: v_mov_b32_e32 v4, 0
+; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, -2.0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, double -2.000000e+00, double -1.000000e+00
+ %ldexp = fmul double %x, %1
+ ret double %ldexp
+}
+
+define double @fmul_select_f64_test7(double %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test7:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xbff00000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, 2.0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test7:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1030-NEXT: v_mov_b32_e32 v4, 0
+; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test7:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1100-NEXT: v_mov_b32_e32 v4, 0
+; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, 2.0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, double 2.000000e+00, double -1.000000e+00
+ %ldexp = fmul double %x, %1
+ ret double %ldexp
+}
+
+define double @fmul_select_f64_test8(double %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xbff00000
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x40100000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test8:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v5, 0x40100000
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1030-NEXT: v_mov_b32_e32 v4, 0
+; GFX1030-NEXT: v_cndmask_b32_e32 v5, 0xbff00000, v5, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test8:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_dual_mov_b32 v5, 0x40100000 :: v_dual_mov_b32 v4, 0
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e32 v5, 0xbff00000, v5, vcc_lo
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, double 4.000000e+00, double -1.000000e+00
+ %ldexp = fmul double %x, %1
+ ret double %ldexp
+}
+
+define <2 x double> @fmul_select_f64_test9(<2 x double> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test9:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v11, 0xbff00000
+; GFX9-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v11, -2.0, vcc
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[9:10]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v11, -2.0, vcc
+; GFX9-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test9:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
+; GFX1030-NEXT: v_mov_b32_e32 v8, 0
+; GFX1030-NEXT: v_cndmask_b32_e64 v11, 0xbff00000, -2.0, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
+; GFX1030-NEXT: v_mov_b32_e32 v10, v8
+; GFX1030-NEXT: v_cndmask_b32_e64 v9, 0xbff00000, -2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[10:11]
+; GFX1030-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test9:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
+; GFX1100-NEXT: v_mov_b32_e32 v8, 0
+; GFX1100-NEXT: v_cndmask_b32_e64 v11, 0xbff00000, -2.0, vcc_lo
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_mov_b32_e32 v10, v8
+; GFX1100-NEXT: v_cndmask_b32_e64 v9, 0xbff00000, -2.0, vcc_lo
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[10:11]
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
+ %1 = select <2 x i1> %bool, <2 x double> <double -2.000000e+00, double -2.000000e+00>, <2 x double> <double -1.000000e+00, double -1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %1
+ ret <2 x double> %ldexp
+}
+
+define <2 x double> @fmul_select_f64_test10(<2 x double> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) {
+; GFX9-LABEL: fmul_select_f64_test10:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-NEXT: v_mov_b32_e32 v9, 0xbff00000
+; GFX9-NEXT: v_mov_b32_e32 v10, 0x3fe00000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6
+; GFX9-NEXT: v_mov_b32_e32 v11, 0x3ff00000
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v9, v10, vcc
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7
+; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[9:10]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v11, 2.0, vcc
+; GFX9-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f64_test10:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
+; GFX1030-NEXT: v_mov_b32_e32 v8, 0
+; GFX1030-NEXT: v_cndmask_b32_e32 v11, 0xbff00000, v9, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
+; GFX1030-NEXT: v_mov_b32_e32 v10, v8
+; GFX1030-NEXT: v_cndmask_b32_e64 v9, 0x3ff00000, 2.0, vcc_lo
+; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[10:11]
+; GFX1030-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f64_test10:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_dual_mov_b32 v9, 0x3fe00000 :: v_dual_mov_b32 v8, 0
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_dual_mov_b32 v10, v8 :: v_dual_cndmask_b32 v11, 0xbff00000, v9
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7
+; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[10:11]
+; GFX1100-NEXT: v_cndmask_b32_e64 v9, 0x3ff00000, 2.0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
+ %1 = select <2 x i1> %bool, <2 x double> <double 0.500000e+00, double 2.000000e+00>, <2 x double> <double -1.000000e+00, double 1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %1
+ ret <2 x double> %ldexp
+}
+
+define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f16_test1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x4000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f16_test1:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v3, 0x4000
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v3, vcc_lo
+; GFX1030-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f16_test1:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_mov_b32_e32 v3, 0x4000
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v3, vcc_lo
+; GFX1100-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, half 2.000000e+00, half 1.000000e+00
+ %ldexp = fmul half %x, %1
+ ret half %ldexp
+}
+
+define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
+; GFX9-LABEL: fmul_select_f16_test2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x3800
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f16_test2:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v3, 0x3800
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v3, vcc_lo
+; GFX1030-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f16_test2:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_mov_b32_e32 v3, 0x3800
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v3, vcc_lo
+; GFX1100-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq i32 %bool.arg1, %bool.arg2
+ %1 = select i1 %bool, half 0.500000e+00, half 1.000000e+00
+ %ldexp = fmul half %x, %1
+ ret half %ldexp
+}
+
+define <2 x half> @fmul_select_f16_test3(<2 x half> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) {
+; GFX9-LABEL: fmul_select_f16_test3:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x3c00
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x4000
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX9-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f16_test3:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v5, 0x4000
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
+; GFX1030-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX1030-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f16_test3:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_mov_b32_e32 v5, 0x4000
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
+; GFX1100-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
+ %1 = select <2 x i1> %bool, <2 x half> <half 2.000000e+00, half 2.000000e+00>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
+ %ldexp = fmul <2 x half> %x, %1
+ ret <2 x half> %ldexp
+}
+
+define <2 x half> @fmul_select_f16_test4(<2 x half> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) {
+; GFX9-LABEL: fmul_select_f16_test4:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x3c00
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x3800
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX9-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1030-LABEL: fmul_select_f16_test4:
+; GFX1030: ; %bb.0:
+; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1030-NEXT: v_mov_b32_e32 v5, 0x3800
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
+; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
+; GFX1030-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX1030-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX1030-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: fmul_select_f16_test4:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_mov_b32_e32 v5, 0x3800
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
+; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
+; GFX1100-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
+ %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
+ %1 = select <2 x i1> %bool, <2 x half> <half 0.500000e+00, half 0.500000e+00>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
+ %ldexp = fmul <2 x half> %x, %1
+ ret <2 x half> %ldexp
+}
>From 575d7ab36e265a9177e9318e953602cdbb6e1cfa Mon Sep 17 00:00:00 2001
From: vikashgu <Vikash.Gupta at amd.com>
Date: Tue, 8 Oct 2024 10:30:33 +0000
Subject: [PATCH 3/3] Refactored test to use named values.
---
.../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 80 +++++++++----------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index 62ba95b9f8a0c0..5405f83b7ab8c3 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -29,8 +29,8 @@ define float @fmul_select_f32_test1(float %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, float 2.000000e+00, float 1.000000e+00
- %ldexp = fmul float %x, %1
+ %y = select i1 %bool, float 2.000000e+00, float 1.000000e+00
+ %ldexp = fmul float %x, %y
ret float %ldexp
}
@@ -60,8 +60,8 @@ define float @fmul_select_f32_test2(float %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, float 0.500000e+00, float 1.000000e+00
- %ldexp = fmul float %x, %1
+ %y = select i1 %bool, float 5.000000e-01, float 1.000000e+00
+ %ldexp = fmul float %x, %y
ret float %ldexp
}
@@ -99,8 +99,8 @@ define <2 x float> @fmul_select_f32_test3(<2 x float> %x, <2 x i32> %bool.arg1,
; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
- %1 = select <2 x i1> %bool, <2 x float> <float 2.000000e+00, float 2.000000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
- %ldexp = fmul <2 x float> %x, %1
+ %y = select <2 x i1> %bool, <2 x float> <float 2.000000e+00, float 2.000000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
+ %ldexp = fmul <2 x float> %x, %y
ret <2 x float> %ldexp
}
@@ -138,8 +138,8 @@ define <2 x float> @fmul_select_f32_test4(<2 x float> %x, <2 x i32> %bool.arg1,
; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
- %1 = select <2 x i1> %bool, <2 x float> <float 0.500000e+00, float 0.500000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
- %ldexp = fmul <2 x float> %x, %1
+ %y = select <2 x i1> %bool, <2 x float> <float 5.000000e-01, float 5.000000e-01>, <2 x float> <float 1.000000e+00, float 1.000000e+00>
+ %ldexp = fmul <2 x float> %x, %y
ret <2 x float> %ldexp
}
@@ -169,8 +169,8 @@ define float @fmul_select_f32_test5(float %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, float -2.000000e+00, float -1.000000e+00
- %ldexp = fmul float %x, %1
+ %y = select i1 %bool, float -2.000000e+00, float -1.000000e+00
+ %ldexp = fmul float %x, %y
ret float %ldexp
}
@@ -204,8 +204,8 @@ define float @fmul_select_f32_test6(float %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, float 3.000000e+00, float 8.000000e+00
- %ldexp = fmul float %x, %1
+ %y = select i1 %bool, float 3.000000e+00, float 8.000000e+00
+ %ldexp = fmul float %x, %y
ret float %ldexp
}
@@ -239,8 +239,8 @@ define double @fmul_select_f64_test1(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, double 2.000000e+00, double 1.000000e+00
- %ldexp = fmul double %x, %1
+ %y = select i1 %bool, double 2.000000e+00, double 1.000000e+00
+ %ldexp = fmul double %x, %y
ret double %ldexp
}
@@ -276,8 +276,8 @@ define double @fmul_select_f64_test2(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, double 0.500000e+00, double 1.000000e+00
- %ldexp = fmul double %x, %1
+ %y = select i1 %bool, double 5.000000e-01, double 1.000000e+00
+ %ldexp = fmul double %x, %y
ret double %ldexp
}
@@ -324,8 +324,8 @@ define <2 x double> @fmul_select_f64_test3(<2 x double> %x, <2 x i32> %bool.arg1
; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
- %1 = select <2 x i1> %bool, <2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
- %ldexp = fmul <2 x double> %x, %1
+ %y = select <2 x i1> %bool, <2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %y
ret <2 x double> %ldexp
}
@@ -373,8 +373,8 @@ define <2 x double> @fmul_select_f64_test4(<2 x double> %x, <2 x i32> %bool.arg1
; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
- %1 = select <2 x i1> %bool, <2 x double> <double 0.500000e+00, double 0.500000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
- %ldexp = fmul <2 x double> %x, %1
+ %y = select <2 x i1> %bool, <2 x double> <double 5.000000e-01, double 5.000000e-01>, <2 x double> <double 1.000000e+00, double 1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %y
ret <2 x double> %ldexp
}
@@ -410,8 +410,8 @@ define double @fmul_select_f64_test5(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, double -0.500000e+00, double -1.000000e+00
- %ldexp = fmul double %x, %1
+ %y = select i1 %bool, double -5.000000e-01, double -1.000000e+00
+ %ldexp = fmul double %x, %y
ret double %ldexp
}
@@ -445,8 +445,8 @@ define double @fmul_select_f64_test6(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, double -2.000000e+00, double -1.000000e+00
- %ldexp = fmul double %x, %1
+ %y = select i1 %bool, double -2.000000e+00, double -1.000000e+00
+ %ldexp = fmul double %x, %y
ret double %ldexp
}
@@ -480,8 +480,8 @@ define double @fmul_select_f64_test7(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, double 2.000000e+00, double -1.000000e+00
- %ldexp = fmul double %x, %1
+ %y = select i1 %bool, double 2.000000e+00, double -1.000000e+00
+ %ldexp = fmul double %x, %y
ret double %ldexp
}
@@ -517,8 +517,8 @@ define double @fmul_select_f64_test8(double %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, double 4.000000e+00, double -1.000000e+00
- %ldexp = fmul double %x, %1
+ %y = select i1 %bool, double 4.000000e+00, double -1.000000e+00
+ %ldexp = fmul double %x, %y
ret double %ldexp
}
@@ -565,8 +565,8 @@ define <2 x double> @fmul_select_f64_test9(<2 x double> %x, <2 x i32> %bool.arg1
; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
- %1 = select <2 x i1> %bool, <2 x double> <double -2.000000e+00, double -2.000000e+00>, <2 x double> <double -1.000000e+00, double -1.000000e+00>
- %ldexp = fmul <2 x double> %x, %1
+ %y = select <2 x i1> %bool, <2 x double> <double -2.000000e+00, double -2.000000e+00>, <2 x double> <double -1.000000e+00, double -1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %y
ret <2 x double> %ldexp
}
@@ -615,8 +615,8 @@ define <2 x double> @fmul_select_f64_test10(<2 x double> %x, <2 x i32> %bool.arg
; GFX1100-NEXT: v_mul_f64 v[2:3], v[2:3], v[8:9]
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
- %1 = select <2 x i1> %bool, <2 x double> <double 0.500000e+00, double 2.000000e+00>, <2 x double> <double -1.000000e+00, double 1.000000e+00>
- %ldexp = fmul <2 x double> %x, %1
+ %y = select <2 x i1> %bool, <2 x double> <double 5.000000e-01, double 2.000000e+00>, <2 x double> <double -1.000000e+00, double 1.000000e+00>
+ %ldexp = fmul <2 x double> %x, %y
ret <2 x double> %ldexp
}
@@ -650,8 +650,8 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX1100-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, half 2.000000e+00, half 1.000000e+00
- %ldexp = fmul half %x, %1
+ %y = select i1 %bool, half 2.000000e+00, half 1.000000e+00
+ %ldexp = fmul half %x, %y
ret half %ldexp
}
@@ -685,8 +685,8 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX1100-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
- %1 = select i1 %bool, half 0.500000e+00, half 1.000000e+00
- %ldexp = fmul half %x, %1
+ %y = select i1 %bool, half 5.000000e-01, half 1.000000e+00
+ %ldexp = fmul half %x, %y
ret half %ldexp
}
@@ -730,8 +730,8 @@ define <2 x half> @fmul_select_f16_test3(<2 x half> %x, <2 x i32> %bool.arg1, <2
; GFX1100-NEXT: v_pk_mul_f16 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
- %1 = select <2 x i1> %bool, <2 x half> <half 2.000000e+00, half 2.000000e+00>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
- %ldexp = fmul <2 x half> %x, %1
+ %y = select <2 x i1> %bool, <2 x half> <half 2.000000e+00, half 2.000000e+00>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
+ %ldexp = fmul <2 x half> %x, %y
ret <2 x half> %ldexp
}
@@ -775,7 +775,7 @@ define <2 x half> @fmul_select_f16_test4(<2 x half> %x, <2 x i32> %bool.arg1, <2
; GFX1100-NEXT: v_pk_mul_f16 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
- %1 = select <2 x i1> %bool, <2 x half> <half 0.500000e+00, half 0.500000e+00>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
- %ldexp = fmul <2 x half> %x, %1
+ %y = select <2 x i1> %bool, <2 x half> <half 5.000000e-01, half 5.000000e-01>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
+ %ldexp = fmul <2 x half> %x, %y
ret <2 x half> %ldexp
}
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