[llvm] [RISCV] Add load/store clustering in post machine schedule (PR #111504)
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Tue Oct 8 01:58:08 PDT 2024
https://github.com/BoyaoWang430 created https://github.com/llvm/llvm-project/pull/111504
#73789 added load clustering and #73796 tried to add store clustering.
If post machine schedule is used, previous cluster of load/store which formed in machine schedule may break. In order to solve this, add load/sotre clustering to post machine schedule.
>From 78e22d51f7d091eee725e7bacd6c66676da58188 Mon Sep 17 00:00:00 2001
From: wangboyao <wangboyao at bytedance.com>
Date: Tue, 8 Oct 2024 16:44:41 +0800
Subject: [PATCH] [RISCV] Add load/store clustering in post machine schedule
If post machine schedule is used, previous cluster of load/store which formed in machine schedule may break. In order to solve this, add load/sotre clustering to post machine schedule.
---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 21 ++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 2dcac1320417c2..0a17a4effc0120 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -99,6 +99,11 @@ static cl::opt<bool> EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(true));
+static cl::opt<bool> EnableMISchedStoreClustering(
+ "riscv-misched-store-clustering", cl::Hidden,
+ cl::desc("Enable store clustering in the machine scheduler"),
+ cl::init(true));
+
static cl::opt<bool> EnableVSETVLIAfterRVVRegAlloc(
"riscv-vsetvl-after-rvv-regalloc", cl::Hidden,
cl::desc("Insert vsetvls after vector register allocation"),
@@ -355,6 +360,22 @@ class RISCVPassConfig : public TargetPassConfig {
return DAG;
}
+ ScheduleDAGInstrs *
+ createPostMachineScheduler(MachineSchedContext *C) const override {
+ ScheduleDAGMI *DAG = nullptr;
+ if (EnableMISchedLoadClustering) {
+ DAG = createGenericSchedPostRA(C);
+ DAG->addMutation(createLoadClusterDAGMutation(
+ DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+ }
+ if (EnableMISchedStoreClustering) {
+ DAG = DAG ? DAG : createGenericSchedPostRA(C);
+ DAG->addMutation(createStoreClusterDAGMutation(
+ DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+ }
+ return DAG;
+ }
+
void addIRPasses() override;
bool addPreISel() override;
void addCodeGenPrepare() override;
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