[llvm] [AMDGPU] In instruction selector, allow copy from physical reg to s1 (PR #96157)

[Jun Wang via llvm-commits]

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@@ -131,6 +131,13 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
   Register SrcReg = Src.getReg();
 
   if (isVCC(DstReg, *MRI)) {
+    // Allow copy from physical register other than SCC to s1.
+    if (SrcReg.isPhysical() && SrcReg != AMDGPU::SCC) {
+      const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg);
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jwanggit86 wrote:

After another look, I think the problem here is quite different from the one in `getInstrMapping()`. Here we are dealing with instruction selection for a COPY from a physical reg to a virtual reg of type s1, such as `%0:vcc(s1) = COPY $sgpr0`. The existing `selectCOPY()` function would reject it. This patch is trying to allow such COPY in some cases. It takes advantage of an existing check of `isVCC()` on the dst reg, and then handles the case when the src is a physical reg. Then patch simply makes sure the src physical reg belongs in the reg class of the dst reg. For example, the above instruction would be allowed on a wave32 target but not on a wave64 target.

In `getInstrMapping()` the reg bank is not selected yet, so based on the type being s1 we set the reg bank to VCCRegBank to allow the mappting to succeed. Here, reg bank is already determined, and `isVCC()` already checks to make sure the type is s1. So I'm not sure what more info should be given to `isVCC()`.

https://github.com/llvm/llvm-project/pull/96157