[llvm] [AMDGPU][MC] Disallow op_sel in v_dot4 and v_dot8 with 4- or 8-bit packed data (PR #100485)

[Jun Wang via llvm-commits]

jwanggit86 wrote:

Here is a summary of my findings from the ISA docs:

- v_dot4_*, v_dot8_* use VOP3P encoding.
- MI100 ISA: Sect 12.10 "VOP3P Instructions", only 3 V_MAD_MIX* instructions use OPSEL.
- MI200 ISA: same as MI100.
- MI300 ISA: same as MI200.
- RDNA1 ISA: No v_dot4_*, v_dot8_*; 3 V_FMA_MIX* instruxtions use OPSEL.
- RDNA2 ISA: 3 V_FMA_MIX* instruxtions use OPSEL.
- RDNA3 ISA: (1) Sect 16.10 "VOP3P Instructions", 3 V_FMA_MIX* instruxtions use OPSEL.
(2) Sect 7.5.1 "Inline Constants with Packed Math", mentions "ignore OPSEL" for dot4_* and dot8_*. So apparently OPSEL
is allowed.

Based on this I'm ok with either of the following: (1) leave assembler/disassembler as is (2) disallow OPSEL for v_dot4_* and v_dot8_* for pre-GFX11 targets, as this patch does. 

@arsenm @Sisyph Please let me know your thoughts.

https://github.com/llvm/llvm-project/pull/100485