[llvm] [SelectionDAG] Legalize vector types for atomic load (PR #111414)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,17 @@
+; RUN: llc %s --print-after-isel --disable-verify 2>&1 | FileCheck %s
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arsenm wrote:

Don't use print-after-isel, or -disable-verify. Check the final isa output (or -stop-after to check real mir), and move to test/CodeGen/X86

https://github.com/llvm/llvm-project/pull/111414