[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)
Finn Plummer via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 7 08:54:26 PDT 2024
https://github.com/inbelic updated https://github.com/llvm/llvm-project/pull/111010
>From 70089645ec5cf62b491a56df96ec46f4328fbc11 Mon Sep 17 00:00:00 2001
From: Finn Plummer <canadienfinn at gmail.com>
Date: Thu, 3 Oct 2024 11:43:51 -0700
Subject: [PATCH 1/7] [HLSL] Implement `WaveReadLaneAt` intrinsic
- create a clang built-in in Builtins.td
- add semantic checking in SemaHLSL.cpp
- link the WaveReadLaneAt api in hlsl_intrinsics.h
- add lowering to spirv backend op GroupNonUniformShuffle
with Scope = 2 (Group) in SPIRVInstructionSelector.cpp
- add tests for HLSL intrinsic lowering to spirv intrinsic in
WaveReadLaneAt.hlsl
- add tests for sema checks in WaveReadLaneAt-errors.hlsl
- add spir-v backend tests in WaveReadLaneAt.ll
---
clang/include/clang/Basic/Builtins.td | 6 +++
clang/lib/CodeGen/CGBuiltin.cpp | 16 ++++++++
clang/lib/CodeGen/CGHLSLRuntime.h | 1 +
clang/lib/Headers/hlsl/hlsl_intrinsics.h | 7 ++++
clang/lib/Sema/SemaHLSL.cpp | 20 ++++++++++
.../CodeGenHLSL/builtins/WaveReadLaneAt.hlsl | 40 +++++++++++++++++++
.../BuiltIns/WaveReadLaneAt-errors.hlsl | 21 ++++++++++
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 1 +
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 15 +++++++
.../SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll | 28 +++++++++++++
10 files changed, 155 insertions(+)
create mode 100644 clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
create mode 100644 clang/test/SemaHLSL/BuiltIns/WaveReadLaneAt-errors.hlsl
create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td
index 8090119e512fbb..eec9acd4d27d7d 100644
--- a/clang/include/clang/Basic/Builtins.td
+++ b/clang/include/clang/Basic/Builtins.td
@@ -4703,6 +4703,12 @@ def HLSLWaveIsFirstLane : LangBuiltin<"HLSL_LANG"> {
let Prototype = "bool()";
}
+def HLSLWaveReadLaneAt : LangBuiltin<"HLSL_LANG"> {
+ let Spellings = ["__builtin_hlsl_wave_read_lane_at"];
+ let Attributes = [NoThrow, Const];
+ let Prototype = "void(...)";
+}
+
def HLSLClamp : LangBuiltin<"HLSL_LANG"> {
let Spellings = ["__builtin_hlsl_elementwise_clamp"];
let Attributes = [NoThrow, Const];
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index da3eca73bfb575..dff56af9282e9d 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18835,6 +18835,22 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic();
return EmitRuntimeCall(Intrinsic::getDeclaration(&CGM.getModule(), ID));
}
+ case Builtin::BI__builtin_hlsl_wave_read_lane_at: {
+ // Due to the use of variadic arguments we must explicitly retreive them and
+ // create our function type.
+ Value *OpExpr = EmitScalarExpr(E->getArg(0));
+ Value *OpIndex = EmitScalarExpr(E->getArg(1));
+ llvm::FunctionType *FT = llvm::FunctionType::get(
+ OpExpr->getType(), ArrayRef{OpExpr->getType(), OpIndex->getType()},
+ false);
+
+ // Get overloaded name
+ std::string name =
+ Intrinsic::getName(CGM.getHLSLRuntime().getWaveReadLaneAtIntrinsic(),
+ ArrayRef{OpExpr->getType()}, &CGM.getModule());
+ return EmitRuntimeCall(CGM.CreateRuntimeFunction(FT, name, {}, false, true),
+ ArrayRef{OpExpr, OpIndex}, "hlsl.wave.read.lane.at");
+ }
case Builtin::BI__builtin_hlsl_elementwise_sign: {
Value *Op0 = EmitScalarExpr(E->getArg(0));
llvm::Type *Xty = Op0->getType();
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h
index a8aabca7348ffb..a639ce2d784f4a 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.h
+++ b/clang/lib/CodeGen/CGHLSLRuntime.h
@@ -87,6 +87,7 @@ class CGHLSLRuntime {
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
+ GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_read_lane_at)
//===----------------------------------------------------------------------===//
// End of reserved area for HLSL intrinsic getters.
diff --git a/clang/lib/Headers/hlsl/hlsl_intrinsics.h b/clang/lib/Headers/hlsl/hlsl_intrinsics.h
index 810a16d75f0228..a7bdc353ae71bf 100644
--- a/clang/lib/Headers/hlsl/hlsl_intrinsics.h
+++ b/clang/lib/Headers/hlsl/hlsl_intrinsics.h
@@ -2015,6 +2015,13 @@ _HLSL_AVAILABILITY(shadermodel, 6.0)
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_is_first_lane)
__attribute__((convergent)) bool WaveIsFirstLane();
+// \brief Returns the value of the expression for the given lane index within
+// the specified wave.
+template <typename T>
+_HLSL_AVAILABILITY(shadermodel, 6.0)
+_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_read_lane_at)
+ __attribute__((convergent)) T WaveReadLaneAt(T, int32_t);
+
//===----------------------------------------------------------------------===//
// sign builtins
//===----------------------------------------------------------------------===//
diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp
index 43cc6c81ae5cb0..d54da3fd8375ed 100644
--- a/clang/lib/Sema/SemaHLSL.cpp
+++ b/clang/lib/Sema/SemaHLSL.cpp
@@ -1956,6 +1956,26 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
return true;
break;
}
+ case Builtin::BI__builtin_hlsl_wave_read_lane_at: {
+ if (SemaRef.checkArgCount(TheCall, 2))
+ return true;
+
+ // Ensure index parameter type can be interpreted as a uint
+ ExprResult Index = TheCall->getArg(1);
+ QualType ArgTyIndex = Index.get()->getType();
+ if (!ArgTyIndex->hasIntegerRepresentation()) {
+ SemaRef.Diag(TheCall->getArg(1)->getBeginLoc(),
+ diag::err_typecheck_convert_incompatible)
+ << ArgTyIndex << SemaRef.Context.UnsignedIntTy << 1 << 0 << 0;
+ return true;
+ }
+
+ // Ensure return type is the same as the input expr type
+ ExprResult Expr = TheCall->getArg(0);
+ QualType ArgTyExpr = Expr.get()->getType();
+ TheCall->setType(ArgTyExpr);
+ break;
+ }
case Builtin::BI__builtin_elementwise_acos:
case Builtin::BI__builtin_elementwise_asin:
case Builtin::BI__builtin_elementwise_atan:
diff --git a/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl b/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
new file mode 100644
index 00000000000000..62319ebc04e2db
--- /dev/null
+++ b/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
@@ -0,0 +1,40 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
+// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV
+
+// Test basic lowering to runtime function call.
+
+// CHECK-LABEL: test_int
+int test_int(int expr, uint idx) {
+ // CHECK-SPIRV: %[[#entry_tok:]] = call token @llvm.experimental.convergence.entry()
+
+ // CHECK-SPIRV: %[[RET:.*]] = call [[TY:.*]] @llvm.spv.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]])
+ // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]])
+
+ // CHECK: ret [[TY]] %[[RET]]
+ return WaveReadLaneAt(expr, idx);
+}
+
+// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.read.lane.at.i32([[TY]], i32) #[[#attr:]]
+// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.read.lane.at.i32([[TY]], i32) #[[#attr:]]
+
+// Test basic lowering to runtime function call with array and float value.
+
+// CHECK-LABEL: test_floatv4
+float4 test_floatv4(float4 expr, uint idx) {
+ // CHECK-SPIRV: %[[#entry_tok1:]] = call token @llvm.experimental.convergence.entry()
+
+ // CHECK-SPIRV: %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]])
+ // CHECK-DXIL: %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]])
+
+ // CHECK: ret [[TY1]] %[[RET1]]
+ return WaveReadLaneAt(expr, idx);
+}
+
+// CHECK-DXIL: declare [[TY1]] @llvm.dx.wave.read.lane.at.v4f32([[TY1]], i32) #[[#attr]]
+// CHECK-SPIRV: declare [[TY1]] @llvm.spv.wave.read.lane.at.v4f32([[TY1]], i32) #[[#attr]]
+
+// CHECK: attributes #[[#attr]] = {{{.*}} convergent {{.*}}}
diff --git a/clang/test/SemaHLSL/BuiltIns/WaveReadLaneAt-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/WaveReadLaneAt-errors.hlsl
new file mode 100644
index 00000000000000..451f2d3a563287
--- /dev/null
+++ b/clang/test/SemaHLSL/BuiltIns/WaveReadLaneAt-errors.hlsl
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected
+
+bool test_too_few_arg() {
+ return __builtin_hlsl_wave_read_lane_at();
+ // expected-error at -1 {{too few arguments to function call, expected 2, have 0}}
+}
+
+float2 test_too_few_arg_1(float2 p0) {
+ return __builtin_hlsl_wave_read_lane_at(p0);
+ // expected-error at -1 {{too few arguments to function call, expected 2, have 1}}
+}
+
+float2 test_too_many_arg(float2 p0) {
+ return __builtin_hlsl_wave_read_lane_at(p0, p0, p0);
+ // expected-error at -1 {{too many arguments to function call, expected 2, have 3}}
+}
+
+float3 test_index_type_check(float3 p0, double idx) {
+ return __builtin_hlsl_wave_read_lane_at(p0, idx);
+ // expected-error at -1 {{passing 'double' to parameter of incompatible type 'unsigned int'}}
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 7ff3d58690ba75..b6ea9ce9b1411e 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -82,5 +82,6 @@ let TargetPrefix = "spv" in {
[llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>],
[IntrNoMem, Commutative] >;
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
+ def int_spv_wave_read_lane_at : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty]>;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 7a565249a342d1..a7279193764fa4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2653,6 +2653,21 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
+ case Intrinsic::spv_wave_read_lane_at: {
+ assert(I.getNumOperands() == 4);
+ assert(I.getOperand(2).isReg());
+ assert(I.getOperand(3).isReg());
+
+ // Defines the execution scope currently 2 for group, see scope table
+ SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
+ return BuildMI(BB, I, I.getDebugLoc(),
+ TII.get(SPIRV::OpGroupNonUniformShuffle))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addUse(I.getOperand(2).getReg())
+ .addUse(I.getOperand(3).getReg())
+ .addUse(GR.getOrCreateConstInt(2, I, IntTy, TII));
+ }
case Intrinsic::spv_step:
return selectStep(ResVReg, ResType, I);
// Discard intrinsics which we do not expect to actually represent code after
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
new file mode 100644
index 00000000000000..e02a2907ee28a0
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
+
+; Test lowering to spir-v backend
+
+; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 2
+; CHECK-DAG: %[[#f32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#expr:]] = OpFunctionParameter %[[#f32]]
+; CHECK-DAG: %[[#idx:]] = OpFunctionParameter %[[#uint]]
+
+define spir_func void @test_1(float %expr, i32 %idx) #0 {
+entry:
+ %0 = call token @llvm.experimental.convergence.entry()
+; CHECK: %[[#ret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#expr]] %[[#idx]] %[[#scope]]
+ %1 = call float @llvm.spv.wave.read.lane.at(float %expr, i32 %idx) [ "convergencectrl"(token %0) ]
+ ret void
+}
+
+declare i32 @__hlsl_wave_get_lane_index() #1
+
+attributes #0 = { convergent norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #1 = { convergent }
+
+!llvm.module.flags = !{!0, !1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
>From e8c5dba828f25c2894980631ae019936a3d9e9f6 Mon Sep 17 00:00:00 2001
From: Finn Plummer <canadienfinn at gmail.com>
Date: Thu, 3 Oct 2024 12:45:50 -0700
Subject: [PATCH 2/7] [DXIL] add WaveReadLaneAt intrinsic for scalars
- add WaveReadLaneAt intrinsic to IntrinsicsDirectX.td and mapping
to DXIL.td
- add test to show scalar functionality
- note that this doesn't include support for the scalarizer to
handle this function will be added in a future pr
---
llvm/include/llvm/IR/IntrinsicsDirectX.td | 1 +
llvm/lib/Target/DirectX/DXIL.td | 10 ++++
llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll | 56 +++++++++++++++++++++
3 files changed, 67 insertions(+)
create mode 100644 llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td
index 555877e7aaf0e5..a12526539e7efe 100644
--- a/llvm/include/llvm/IR/IntrinsicsDirectX.td
+++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td
@@ -83,6 +83,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
+def int_dx_wave_read_lane_at : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent]>;
def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, LLVMMatchType<0>], [IntrNoMem]>;
}
diff --git a/llvm/lib/Target/DirectX/DXIL.td b/llvm/lib/Target/DirectX/DXIL.td
index 9aa0af3e3a6b17..7283d069988123 100644
--- a/llvm/lib/Target/DirectX/DXIL.td
+++ b/llvm/lib/Target/DirectX/DXIL.td
@@ -801,3 +801,13 @@ def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
let stages = [Stages<DXIL1_0, [all_stages]>];
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
}
+
+def WaveReadLaneAt: DXILOp<117, waveIsFirstLane> {
+ let Doc = "returns the value from the specified lane";
+ let LLVMIntrinsic = int_dx_wave_read_lane_at;
+ let arguments = [OverloadTy, Int32Ty];
+ let result = OverloadTy;
+ let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty]>];
+ let stages = [Stages<DXIL1_0, [all_stages]>];
+ let attributes = [Attributes<DXIL1_0, [ReadNone]>];
+}
diff --git a/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll b/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll
new file mode 100644
index 00000000000000..7f524923136349
--- /dev/null
+++ b/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll
@@ -0,0 +1,56 @@
+; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s
+
+; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op
+
+define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK: call half @dx.op.waveReadLaneAt.f16(i32 117, half %expr, i32 %idx)
+ %ret = call half @llvm.dx.wave.read.lane.at.f16(half %expr, i32 %idx)
+ ret half %ret
+}
+
+define noundef float @wave_rla_float(float noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK: call float @dx.op.waveReadLaneAt.f32(i32 117, float %expr, i32 %idx)
+ %ret = call float @llvm.dx.wave.read.lane.at(float %expr, i32 %idx)
+ ret float %ret
+}
+
+define noundef double @wave_rla_double(double noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK: call double @dx.op.waveReadLaneAt.f64(i32 117, double %expr, i32 %idx)
+ %ret = call double @llvm.dx.wave.read.lane.at(double %expr, i32 %idx)
+ ret double %ret
+}
+
+define noundef i1 @wave_rla_i1(i1 noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK: call i1 @dx.op.waveReadLaneAt.i1(i32 117, i1 %expr, i32 %idx)
+ %ret = call i1 @llvm.dx.wave.read.lane.at.i1(i1 %expr, i32 %idx)
+ ret i1 %ret
+}
+
+define noundef i16 @wave_rla_i16(i16 noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK: call i16 @dx.op.waveReadLaneAt.i16(i32 117, i16 %expr, i32 %idx)
+ %ret = call i16 @llvm.dx.wave.read.lane.at.i16(i16 %expr, i32 %idx)
+ ret i16 %ret
+}
+
+define noundef i32 @wave_rla_i32(i32 noundef %expr, i32 noundef %idx) #0 {
+entry:
+; CHECK: call i32 @dx.op.waveReadLaneAt.i32(i32 117, i32 %expr, i32 %idx)
+ %ret = call i32 @llvm.dx.wave.read.lane.at.i32(i32 %expr, i32 %idx)
+ ret i32 %ret
+}
+
+declare half @llvm.dx.wave.read.lane.at.f16(half, i32) #1
+declare float @llvm.dx.wave.read.lane.at.f32(float, i32) #1
+declare double @llvm.dx.wave.read.lane.at.f64(double, i32) #1
+
+declare i1 @llvm.dx.wave.read.lane.at.i1(i1, i32) #1
+declare i16 @llvm.dx.wave.read.lane.at.i16(i16, i32) #1
+declare i32 @llvm.dx.wave.read.lane.at.i32(i32, i32) #1
+
+attributes #0 = { norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #1 = { nocallback nofree nosync nounwind willreturn }
>From 1b0746f152b4eaa4f6e661787503fc6f7d1fdc72 Mon Sep 17 00:00:00 2001
From: Finn Plummer <canadienfinn at gmail.com>
Date: Fri, 4 Oct 2024 08:05:38 -0700
Subject: [PATCH 3/7] review comments
- add check for "convergencectrl" token in hlsl -> spirv intrinsic
- correct the execution scope of the spirv instruction, add
description
- fix typo
---
clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl | 4 ++--
llvm/lib/Target/DirectX/DXIL.td | 2 +-
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 5 +++--
llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll | 2 +-
4 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl b/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
index 62319ebc04e2db..ce2b0fce3c32a3 100644
--- a/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
@@ -11,7 +11,7 @@
int test_int(int expr, uint idx) {
// CHECK-SPIRV: %[[#entry_tok:]] = call token @llvm.experimental.convergence.entry()
- // CHECK-SPIRV: %[[RET:.*]] = call [[TY:.*]] @llvm.spv.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]])
+ // CHECK-SPIRV: %[[RET:.*]] = call [[TY:.*]] @llvm.spv.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok]]) ]
// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]])
// CHECK: ret [[TY]] %[[RET]]
@@ -27,7 +27,7 @@ int test_int(int expr, uint idx) {
float4 test_floatv4(float4 expr, uint idx) {
// CHECK-SPIRV: %[[#entry_tok1:]] = call token @llvm.experimental.convergence.entry()
- // CHECK-SPIRV: %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]])
+ // CHECK-SPIRV: %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok1]]) ]
// CHECK-DXIL: %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]])
// CHECK: ret [[TY1]] %[[RET1]]
diff --git a/llvm/lib/Target/DirectX/DXIL.td b/llvm/lib/Target/DirectX/DXIL.td
index 7283d069988123..fbb9cd41bdcc1e 100644
--- a/llvm/lib/Target/DirectX/DXIL.td
+++ b/llvm/lib/Target/DirectX/DXIL.td
@@ -802,7 +802,7 @@ def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
}
-def WaveReadLaneAt: DXILOp<117, waveIsFirstLane> {
+def WaveReadLaneAt: DXILOp<117, waveReadLaneAt> {
let Doc = "returns the value from the specified lane";
let LLVMIntrinsic = int_dx_wave_read_lane_at;
let arguments = [OverloadTy, Int32Ty];
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index a7279193764fa4..680965c22400d1 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2658,7 +2658,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
assert(I.getOperand(2).isReg());
assert(I.getOperand(3).isReg());
- // Defines the execution scope currently 2 for group, see scope table
+ // IntTy is used to define the execution scope, set to 3 to denote a
+ // cross-lane interaction equivalent to a SPIR-V subgroup.
SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
return BuildMI(BB, I, I.getDebugLoc(),
TII.get(SPIRV::OpGroupNonUniformShuffle))
@@ -2666,7 +2667,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(I.getOperand(2).getReg())
.addUse(I.getOperand(3).getReg())
- .addUse(GR.getOrCreateConstInt(2, I, IntTy, TII));
+ .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
case Intrinsic::spv_step:
return selectStep(ResVReg, ResType, I);
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
index e02a2907ee28a0..df6643c605d129 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
@@ -4,7 +4,7 @@
; Test lowering to spir-v backend
; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0
-; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 2
+; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 3
; CHECK-DAG: %[[#f32:]] = OpTypeFloat 32
; CHECK-DAG: %[[#expr:]] = OpFunctionParameter %[[#f32]]
; CHECK-DAG: %[[#idx:]] = OpFunctionParameter %[[#uint]]
>From 473150df115944655bbe5d23bbfe8b5e1106c604 Mon Sep 17 00:00:00 2001
From: Finn Plummer <canadienfinn at gmail.com>
Date: Fri, 4 Oct 2024 09:53:06 -0700
Subject: [PATCH 4/7] review comments
- extend spirv testcase to include i32 and vector of bools
---
.../SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll | 20 ++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
index df6643c605d129..c40fed4f860038 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
@@ -6,18 +6,28 @@
; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0
; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 3
; CHECK-DAG: %[[#f32:]] = OpTypeFloat 32
-; CHECK-DAG: %[[#expr:]] = OpFunctionParameter %[[#f32]]
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#v4_bool:]] = OpTypeVector %[[#bool]] 4
+; CHECK-DAG: %[[#fexpr:]] = OpFunctionParameter %[[#f32]]
+; CHECK-DAG: %[[#iexpr:]] = OpFunctionParameter %[[#uint]]
; CHECK-DAG: %[[#idx:]] = OpFunctionParameter %[[#uint]]
+; CHECK-DAG: %[[#vbexpr:]] = OpFunctionParameter %[[#v4_bool]]
-define spir_func void @test_1(float %expr, i32 %idx) #0 {
+define spir_func void @test_1(float %fexpr, i32 %iexpr, <4 x i1> %vbexpr, i32 %idx) #0 {
entry:
%0 = call token @llvm.experimental.convergence.entry()
-; CHECK: %[[#ret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#expr]] %[[#idx]] %[[#scope]]
- %1 = call float @llvm.spv.wave.read.lane.at(float %expr, i32 %idx) [ "convergencectrl"(token %0) ]
+; CHECK: %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#fexpr]] %[[#idx]] %[[#scope]]
+ %1 = call float @llvm.spv.wave.read.lane.at.f32(float %fexpr, i32 %idx) [ "convergencectrl"(token %0) ]
+; CHECK: %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#iexpr]] %[[#idx]] %[[#scope]]
+ %2 = call i32 @llvm.spv.wave.read.lane.at.i32(i32 %iexpr, i32 %idx) [ "convergencectrl"(token %0) ]
+; CHECK: %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#vbexpr]] %[[#idx]] %[[#scope]]
+ %3 = call <4 x i1> @llvm.spv.wave.read.lane.at.v4i1(<4 x i1> %vbexpr, i32 %idx) [ "convergencectrl"(token %0) ]
ret void
}
-declare i32 @__hlsl_wave_get_lane_index() #1
+declare float @__hlsl_wave_read_lane_at.f32(float, i32) #1
+declare i32 @__hlsl_wave_read_lane_at.i32(i32, i32) #1
+declare <4 x i1> @__hlsl_wave_read_lane_at.v4i1(<4 x i1>, i32) #1
attributes #0 = { convergent norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
attributes #1 = { convergent }
>From 484b2089ae9f0a0fae09b6d68b70171f1007bade Mon Sep 17 00:00:00 2001
From: Finn Plummer <canadienfinn at gmail.com>
Date: Fri, 4 Oct 2024 15:04:36 -0700
Subject: [PATCH 5/7] review comments
- remove unneeded attributes from test functions
- provide context to parameters in CGBuiltin
- update intrinsic naming for clarity
---
clang/lib/CodeGen/CGBuiltin.cpp | 6 ++-
.../CodeGenHLSL/builtins/WaveReadLaneAt.hlsl | 4 --
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 41 +++++++++++--------
llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll | 27 ++++++------
.../SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll | 23 ++++-------
5 files changed, 48 insertions(+), 53 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index dff56af9282e9d..fef9b1667241ee 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18848,8 +18848,10 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
std::string name =
Intrinsic::getName(CGM.getHLSLRuntime().getWaveReadLaneAtIntrinsic(),
ArrayRef{OpExpr->getType()}, &CGM.getModule());
- return EmitRuntimeCall(CGM.CreateRuntimeFunction(FT, name, {}, false, true),
- ArrayRef{OpExpr, OpIndex}, "hlsl.wave.read.lane.at");
+ return EmitRuntimeCall(CGM.CreateRuntimeFunction(FT, name, {},
+ /*Local=*/false,
+ /*AssumeConvergent=*/true),
+ ArrayRef{OpExpr, OpIndex}, "hlsl.waveReadLaneAt");
}
case Builtin::BI__builtin_hlsl_elementwise_sign: {
Value *Op0 = EmitScalarExpr(E->getArg(0));
diff --git a/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl b/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
index ce2b0fce3c32a3..e0c0e48bab7941 100644
--- a/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
@@ -10,10 +10,8 @@
// CHECK-LABEL: test_int
int test_int(int expr, uint idx) {
// CHECK-SPIRV: %[[#entry_tok:]] = call token @llvm.experimental.convergence.entry()
-
// CHECK-SPIRV: %[[RET:.*]] = call [[TY:.*]] @llvm.spv.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok]]) ]
// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]])
-
// CHECK: ret [[TY]] %[[RET]]
return WaveReadLaneAt(expr, idx);
}
@@ -26,10 +24,8 @@ int test_int(int expr, uint idx) {
// CHECK-LABEL: test_floatv4
float4 test_floatv4(float4 expr, uint idx) {
// CHECK-SPIRV: %[[#entry_tok1:]] = call token @llvm.experimental.convergence.entry()
-
// CHECK-SPIRV: %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok1]]) ]
// CHECK-DXIL: %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]])
-
// CHECK: ret [[TY1]] %[[RET1]]
return WaveReadLaneAt(expr, idx);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 680965c22400d1..d6a2717f557d9f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -244,6 +244,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectSpvThreadId(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
+ bool selectWaveReadLaneAt(Register ResVReg, const SPIRVType *ResType,
+ MachineInstr &I) const;
+
bool selectStep(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
@@ -1853,6 +1856,26 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveReadLaneAt(Register ResVReg,
+ const SPIRVType *ResType,
+ MachineInstr &I) const {
+ assert(I.getNumOperands() == 4);
+ assert(I.getOperand(2).isReg());
+ assert(I.getOperand(3).isReg());
+ MachineBasicBlock &BB = *I.getParent();
+
+ // IntTy is used to define the execution scope, set to 3 to denote a
+ // cross-lane interaction equivalent to a SPIR-V subgroup.
+ SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
+ return BuildMI(BB, I, I.getDebugLoc(),
+ TII.get(SPIRV::OpGroupNonUniformShuffle))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addUse(I.getOperand(2).getReg())
+ .addUse(I.getOperand(3).getReg())
+ .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
+}
+
bool SPIRVInstructionSelector::selectStep(Register ResVReg,
const SPIRVType *ResType,
MachineInstr &I) const {
@@ -2653,22 +2676,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
- case Intrinsic::spv_wave_read_lane_at: {
- assert(I.getNumOperands() == 4);
- assert(I.getOperand(2).isReg());
- assert(I.getOperand(3).isReg());
-
- // IntTy is used to define the execution scope, set to 3 to denote a
- // cross-lane interaction equivalent to a SPIR-V subgroup.
- SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
- return BuildMI(BB, I, I.getDebugLoc(),
- TII.get(SPIRV::OpGroupNonUniformShuffle))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addUse(I.getOperand(2).getReg())
- .addUse(I.getOperand(3).getReg())
- .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
- }
+ case Intrinsic::spv_wave_read_lane_at:
+ return selectWaveReadLaneAt(ResVReg, ResType, I);
case Intrinsic::spv_step:
return selectStep(ResVReg, ResType, I);
// Discard intrinsics which we do not expect to actually represent code after
diff --git a/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll b/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll
index 7f524923136349..4d2d72e064e61e 100644
--- a/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll
+++ b/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll
@@ -2,55 +2,52 @@
; Test that for scalar values, WaveReadLaneAt maps down to the DirectX op
-define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) #0 {
+define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call half @dx.op.waveReadLaneAt.f16(i32 117, half %expr, i32 %idx)
%ret = call half @llvm.dx.wave.read.lane.at.f16(half %expr, i32 %idx)
ret half %ret
}
-define noundef float @wave_rla_float(float noundef %expr, i32 noundef %idx) #0 {
+define noundef float @wave_rla_float(float noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call float @dx.op.waveReadLaneAt.f32(i32 117, float %expr, i32 %idx)
%ret = call float @llvm.dx.wave.read.lane.at(float %expr, i32 %idx)
ret float %ret
}
-define noundef double @wave_rla_double(double noundef %expr, i32 noundef %idx) #0 {
+define noundef double @wave_rla_double(double noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call double @dx.op.waveReadLaneAt.f64(i32 117, double %expr, i32 %idx)
%ret = call double @llvm.dx.wave.read.lane.at(double %expr, i32 %idx)
ret double %ret
}
-define noundef i1 @wave_rla_i1(i1 noundef %expr, i32 noundef %idx) #0 {
+define noundef i1 @wave_rla_i1(i1 noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call i1 @dx.op.waveReadLaneAt.i1(i32 117, i1 %expr, i32 %idx)
%ret = call i1 @llvm.dx.wave.read.lane.at.i1(i1 %expr, i32 %idx)
ret i1 %ret
}
-define noundef i16 @wave_rla_i16(i16 noundef %expr, i32 noundef %idx) #0 {
+define noundef i16 @wave_rla_i16(i16 noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call i16 @dx.op.waveReadLaneAt.i16(i32 117, i16 %expr, i32 %idx)
%ret = call i16 @llvm.dx.wave.read.lane.at.i16(i16 %expr, i32 %idx)
ret i16 %ret
}
-define noundef i32 @wave_rla_i32(i32 noundef %expr, i32 noundef %idx) #0 {
+define noundef i32 @wave_rla_i32(i32 noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call i32 @dx.op.waveReadLaneAt.i32(i32 117, i32 %expr, i32 %idx)
%ret = call i32 @llvm.dx.wave.read.lane.at.i32(i32 %expr, i32 %idx)
ret i32 %ret
}
-declare half @llvm.dx.wave.read.lane.at.f16(half, i32) #1
-declare float @llvm.dx.wave.read.lane.at.f32(float, i32) #1
-declare double @llvm.dx.wave.read.lane.at.f64(double, i32) #1
+declare half @llvm.dx.wave.read.lane.at.f16(half, i32)
+declare float @llvm.dx.wave.read.lane.at.f32(float, i32)
+declare double @llvm.dx.wave.read.lane.at.f64(double, i32)
-declare i1 @llvm.dx.wave.read.lane.at.i1(i1, i32) #1
-declare i16 @llvm.dx.wave.read.lane.at.i16(i16, i32) #1
-declare i32 @llvm.dx.wave.read.lane.at.i32(i32, i32) #1
-
-attributes #0 = { norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-attributes #1 = { nocallback nofree nosync nounwind willreturn }
+declare i1 @llvm.dx.wave.read.lane.at.i1(i1, i32)
+declare i16 @llvm.dx.wave.read.lane.at.i16(i16, i32)
+declare i32 @llvm.dx.wave.read.lane.at.i32(i32, i32)
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
index c40fed4f860038..506df2e0572c5d 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
@@ -13,26 +13,17 @@
; CHECK-DAG: %[[#idx:]] = OpFunctionParameter %[[#uint]]
; CHECK-DAG: %[[#vbexpr:]] = OpFunctionParameter %[[#v4_bool]]
-define spir_func void @test_1(float %fexpr, i32 %iexpr, <4 x i1> %vbexpr, i32 %idx) #0 {
+define spir_func void @test_1(float %fexpr, i32 %iexpr, <4 x i1> %vbexpr, i32 %idx) {
entry:
- %0 = call token @llvm.experimental.convergence.entry()
; CHECK: %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#fexpr]] %[[#idx]] %[[#scope]]
- %1 = call float @llvm.spv.wave.read.lane.at.f32(float %fexpr, i32 %idx) [ "convergencectrl"(token %0) ]
+ %0 = call float @llvm.spv.wave.read.lane.at.f32(float %fexpr, i32 %idx)
; CHECK: %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#iexpr]] %[[#idx]] %[[#scope]]
- %2 = call i32 @llvm.spv.wave.read.lane.at.i32(i32 %iexpr, i32 %idx) [ "convergencectrl"(token %0) ]
+ %1 = call i32 @llvm.spv.wave.read.lane.at.i32(i32 %iexpr, i32 %idx)
; CHECK: %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#vbexpr]] %[[#idx]] %[[#scope]]
- %3 = call <4 x i1> @llvm.spv.wave.read.lane.at.v4i1(<4 x i1> %vbexpr, i32 %idx) [ "convergencectrl"(token %0) ]
+ %2 = call <4 x i1> @llvm.spv.wave.read.lane.at.v4i1(<4 x i1> %vbexpr, i32 %idx)
ret void
}
-declare float @__hlsl_wave_read_lane_at.f32(float, i32) #1
-declare i32 @__hlsl_wave_read_lane_at.i32(i32, i32) #1
-declare <4 x i1> @__hlsl_wave_read_lane_at.v4i1(<4 x i1>, i32) #1
-
-attributes #0 = { convergent norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-attributes #1 = { convergent }
-
-!llvm.module.flags = !{!0, !1}
-
-!0 = !{i32 1, !"wchar_size", i32 4}
-!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
+declare float @__hlsl_wave_read_lane_at.f32(float, i32)
+declare i32 @__hlsl_wave_read_lane_at.i32(i32, i32)
+declare <4 x i1> @__hlsl_wave_read_lane_at.v4i1(<4 x i1>, i32)
>From dc3fc0bd141735c262fa6fcf72aaa5243d70f459 Mon Sep 17 00:00:00 2001
From: Finn Plummer <canadienfinn at gmail.com>
Date: Fri, 4 Oct 2024 15:35:56 -0700
Subject: [PATCH 6/7] review comments:
- change spv/dx intrinsics naming from wave_read_lane_at to
waveReadLaneAt
---
clang/lib/CodeGen/CGHLSLRuntime.h | 2 +-
.../CodeGenHLSL/builtins/WaveReadLaneAt.hlsl | 16 ++++++-------
llvm/include/llvm/IR/IntrinsicsDirectX.td | 2 +-
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 2 +-
llvm/lib/Target/DirectX/DXIL.td | 2 +-
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 2 +-
llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll | 24 +++++++++----------
.../SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll | 12 +++++-----
8 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h
index a639ce2d784f4a..1fa89d417729f5 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.h
+++ b/clang/lib/CodeGen/CGHLSLRuntime.h
@@ -87,7 +87,7 @@ class CGHLSLRuntime {
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
- GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_read_lane_at)
+ GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, waveReadLaneAt)
//===----------------------------------------------------------------------===//
// End of reserved area for HLSL intrinsic getters.
diff --git a/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl b/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
index e0c0e48bab7941..0162c0bb874ca9 100644
--- a/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
@@ -10,27 +10,27 @@
// CHECK-LABEL: test_int
int test_int(int expr, uint idx) {
// CHECK-SPIRV: %[[#entry_tok:]] = call token @llvm.experimental.convergence.entry()
- // CHECK-SPIRV: %[[RET:.*]] = call [[TY:.*]] @llvm.spv.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok]]) ]
- // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]])
+ // CHECK-SPIRV: %[[RET:.*]] = call [[TY:.*]] @llvm.spv.waveReadLaneAt.i32([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok]]) ]
+ // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.waveReadLaneAt.i32([[TY]] %[[#]], i32 %[[#]])
// CHECK: ret [[TY]] %[[RET]]
return WaveReadLaneAt(expr, idx);
}
-// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.read.lane.at.i32([[TY]], i32) #[[#attr:]]
-// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.read.lane.at.i32([[TY]], i32) #[[#attr:]]
+// CHECK-DXIL: declare [[TY]] @llvm.dx.waveReadLaneAt.i32([[TY]], i32) #[[#attr:]]
+// CHECK-SPIRV: declare [[TY]] @llvm.spv.waveReadLaneAt.i32([[TY]], i32) #[[#attr:]]
// Test basic lowering to runtime function call with array and float value.
// CHECK-LABEL: test_floatv4
float4 test_floatv4(float4 expr, uint idx) {
// CHECK-SPIRV: %[[#entry_tok1:]] = call token @llvm.experimental.convergence.entry()
- // CHECK-SPIRV: %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok1]]) ]
- // CHECK-DXIL: %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]])
+ // CHECK-SPIRV: %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.waveReadLaneAt.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok1]]) ]
+ // CHECK-DXIL: %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.waveReadLaneAt.v4f32([[TY1]] %[[#]], i32 %[[#]])
// CHECK: ret [[TY1]] %[[RET1]]
return WaveReadLaneAt(expr, idx);
}
-// CHECK-DXIL: declare [[TY1]] @llvm.dx.wave.read.lane.at.v4f32([[TY1]], i32) #[[#attr]]
-// CHECK-SPIRV: declare [[TY1]] @llvm.spv.wave.read.lane.at.v4f32([[TY1]], i32) #[[#attr]]
+// CHECK-DXIL: declare [[TY1]] @llvm.dx.waveReadLaneAt.v4f32([[TY1]], i32) #[[#attr]]
+// CHECK-SPIRV: declare [[TY1]] @llvm.spv.waveReadLaneAt.v4f32([[TY1]], i32) #[[#attr]]
// CHECK: attributes #[[#attr]] = {{{.*}} convergent {{.*}}}
diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td
index a12526539e7efe..36dcdc8992087e 100644
--- a/llvm/include/llvm/IR/IntrinsicsDirectX.td
+++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td
@@ -83,7 +83,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
-def int_dx_wave_read_lane_at : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent]>;
+def int_dx_waveReadLaneAt : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent]>;
def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, LLVMMatchType<0>], [IntrNoMem]>;
}
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index b6ea9ce9b1411e..19ed7f4a3970b5 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -82,6 +82,6 @@ let TargetPrefix = "spv" in {
[llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>],
[IntrNoMem, Commutative] >;
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
- def int_spv_wave_read_lane_at : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent]>;
+ def int_spv_waveReadLaneAt : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty]>;
}
diff --git a/llvm/lib/Target/DirectX/DXIL.td b/llvm/lib/Target/DirectX/DXIL.td
index fbb9cd41bdcc1e..2e307a0ae16da5 100644
--- a/llvm/lib/Target/DirectX/DXIL.td
+++ b/llvm/lib/Target/DirectX/DXIL.td
@@ -804,7 +804,7 @@ def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
def WaveReadLaneAt: DXILOp<117, waveReadLaneAt> {
let Doc = "returns the value from the specified lane";
- let LLVMIntrinsic = int_dx_wave_read_lane_at;
+ let LLVMIntrinsic = int_dx_waveReadLaneAt;
let arguments = [OverloadTy, Int32Ty];
let result = OverloadTy;
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty]>];
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index d6a2717f557d9f..229d57e47626bf 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2676,7 +2676,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
- case Intrinsic::spv_wave_read_lane_at:
+ case Intrinsic::spv_waveReadLaneAt:
return selectWaveReadLaneAt(ResVReg, ResType, I);
case Intrinsic::spv_step:
return selectStep(ResVReg, ResType, I);
diff --git a/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll b/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll
index 4d2d72e064e61e..1a1c426a4e5557 100644
--- a/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll
+++ b/llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll
@@ -5,49 +5,49 @@
define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call half @dx.op.waveReadLaneAt.f16(i32 117, half %expr, i32 %idx)
- %ret = call half @llvm.dx.wave.read.lane.at.f16(half %expr, i32 %idx)
+ %ret = call half @llvm.dx.waveReadLaneAt.f16(half %expr, i32 %idx)
ret half %ret
}
define noundef float @wave_rla_float(float noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call float @dx.op.waveReadLaneAt.f32(i32 117, float %expr, i32 %idx)
- %ret = call float @llvm.dx.wave.read.lane.at(float %expr, i32 %idx)
+ %ret = call float @llvm.dx.waveReadLaneAt(float %expr, i32 %idx)
ret float %ret
}
define noundef double @wave_rla_double(double noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call double @dx.op.waveReadLaneAt.f64(i32 117, double %expr, i32 %idx)
- %ret = call double @llvm.dx.wave.read.lane.at(double %expr, i32 %idx)
+ %ret = call double @llvm.dx.waveReadLaneAt(double %expr, i32 %idx)
ret double %ret
}
define noundef i1 @wave_rla_i1(i1 noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call i1 @dx.op.waveReadLaneAt.i1(i32 117, i1 %expr, i32 %idx)
- %ret = call i1 @llvm.dx.wave.read.lane.at.i1(i1 %expr, i32 %idx)
+ %ret = call i1 @llvm.dx.waveReadLaneAt.i1(i1 %expr, i32 %idx)
ret i1 %ret
}
define noundef i16 @wave_rla_i16(i16 noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call i16 @dx.op.waveReadLaneAt.i16(i32 117, i16 %expr, i32 %idx)
- %ret = call i16 @llvm.dx.wave.read.lane.at.i16(i16 %expr, i32 %idx)
+ %ret = call i16 @llvm.dx.waveReadLaneAt.i16(i16 %expr, i32 %idx)
ret i16 %ret
}
define noundef i32 @wave_rla_i32(i32 noundef %expr, i32 noundef %idx) {
entry:
; CHECK: call i32 @dx.op.waveReadLaneAt.i32(i32 117, i32 %expr, i32 %idx)
- %ret = call i32 @llvm.dx.wave.read.lane.at.i32(i32 %expr, i32 %idx)
+ %ret = call i32 @llvm.dx.waveReadLaneAt.i32(i32 %expr, i32 %idx)
ret i32 %ret
}
-declare half @llvm.dx.wave.read.lane.at.f16(half, i32)
-declare float @llvm.dx.wave.read.lane.at.f32(float, i32)
-declare double @llvm.dx.wave.read.lane.at.f64(double, i32)
+declare half @llvm.dx.waveReadLaneAt.f16(half, i32)
+declare float @llvm.dx.waveReadLaneAt.f32(float, i32)
+declare double @llvm.dx.waveReadLaneAt.f64(double, i32)
-declare i1 @llvm.dx.wave.read.lane.at.i1(i1, i32)
-declare i16 @llvm.dx.wave.read.lane.at.i16(i16, i32)
-declare i32 @llvm.dx.wave.read.lane.at.i32(i32, i32)
+declare i1 @llvm.dx.waveReadLaneAt.i1(i1, i32)
+declare i16 @llvm.dx.waveReadLaneAt.i16(i16, i32)
+declare i32 @llvm.dx.waveReadLaneAt.i32(i32, i32)
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
index 506df2e0572c5d..88f3ddc9f5bc55 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll
@@ -16,14 +16,14 @@
define spir_func void @test_1(float %fexpr, i32 %iexpr, <4 x i1> %vbexpr, i32 %idx) {
entry:
; CHECK: %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#fexpr]] %[[#idx]] %[[#scope]]
- %0 = call float @llvm.spv.wave.read.lane.at.f32(float %fexpr, i32 %idx)
+ %0 = call float @llvm.spv.waveReadLaneAt.f32(float %fexpr, i32 %idx)
; CHECK: %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#iexpr]] %[[#idx]] %[[#scope]]
- %1 = call i32 @llvm.spv.wave.read.lane.at.i32(i32 %iexpr, i32 %idx)
+ %1 = call i32 @llvm.spv.waveReadLaneAt.i32(i32 %iexpr, i32 %idx)
; CHECK: %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#vbexpr]] %[[#idx]] %[[#scope]]
- %2 = call <4 x i1> @llvm.spv.wave.read.lane.at.v4i1(<4 x i1> %vbexpr, i32 %idx)
+ %2 = call <4 x i1> @llvm.spv.waveReadLaneAt.v4i1(<4 x i1> %vbexpr, i32 %idx)
ret void
}
-declare float @__hlsl_wave_read_lane_at.f32(float, i32)
-declare i32 @__hlsl_wave_read_lane_at.i32(i32, i32)
-declare <4 x i1> @__hlsl_wave_read_lane_at.v4i1(<4 x i1>, i32)
+declare float @__hlsl_waveReadLaneAt.f32(float, i32)
+declare i32 @__hlsl_waveReadLaneAt.i32(i32, i32)
+declare <4 x i1> @__hlsl_waveReadLaneAt.v4i1(<4 x i1>, i32)
>From 5a2c5945ec293cd0d217e827b8e155b70e0af02b Mon Sep 17 00:00:00 2001
From: Finn Plummer <canadienfinn at gmail.com>
Date: Mon, 7 Oct 2024 08:53:13 -0700
Subject: [PATCH 7/7] review comments:
- add `IntrNoMem` to intrinsics to denote no memory access
---
llvm/include/llvm/IR/IntrinsicsDirectX.td | 2 +-
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td
index 36dcdc8992087e..ab0e2f187bc23f 100644
--- a/llvm/include/llvm/IR/IntrinsicsDirectX.td
+++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td
@@ -83,7 +83,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
-def int_dx_waveReadLaneAt : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent]>;
+def int_dx_waveReadLaneAt : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, LLVMMatchType<0>], [IntrNoMem]>;
}
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 19ed7f4a3970b5..0b674d1569f8f9 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -82,6 +82,6 @@ let TargetPrefix = "spv" in {
[llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>],
[IntrNoMem, Commutative] >;
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
- def int_spv_waveReadLaneAt : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent]>;
+ def int_spv_waveReadLaneAt : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty]>;
}
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