[llvm] [CodeGen] Use 128bits for LaneBitmask. (PR #111157)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> That said, I'm at wits end of how to represent this in TableGen, because with every try and turn I run into some TableGen assertion failure. I've tried using `ComposedSubRegIndex` to no avail. Not sure if there's some TableGen bugs I'm running into, or whether I'm just not describing this the right way using the existing constructs.

Yes, tablegen isn't the best software 

> 
> Could you give me some suggestions on what the right way is to represent it?
>

I think above you described it correctly, it's a matter of just making it work

> 
> I do wonder if extending the number of bits for LaneBitmask is such a big problem in practice. I suspect at some point we'll need to have a wider bitmask anyway, given that all registers for a target use the same encoding space in lanebitmask. As was pointed out for AMDGPU it's already at the limit.

This is used in the inner loops of everything involving register liveness, which is already the slowest part in the slowest compiles. I think increasing this should only be done as a last resort. 

https://github.com/llvm/llvm-project/pull/111157