[llvm] 35f1966 - [RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (#111308)

[via llvm-commits]

Author: Craig Topper
Date: 2024-10-06T19:27:18-07:00
New Revision: 35f196645079cf499bdc48863ed5a42a0bc375de

URL: https://github.com/llvm/llvm-project/commit/35f196645079cf499bdc48863ed5a42a0bc375de
DIFF: https://github.com/llvm/llvm-project/commit/35f196645079cf499bdc48863ed5a42a0bc375de.diff

LOG: [RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (#111308)

If we disassemble other rounding modes, we'll print something that can't
be parsed.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 7c8206cb44dec2..be0a61263297e4 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -375,6 +375,16 @@ static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
+                                 const MCDisassembler *Decoder) {
+  assert(isUInt<3>(Imm) && "Invalid immediate");
+  if (Imm != RISCVFPRndMode::RTZ)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(Imm));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder);

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8cc5127f0e17a5..f62a7e1221122b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -47,7 +47,7 @@ def RTZArg : AsmOperandClass {
 def rtzarg : Operand<XLenVT> {
   let ParserMatchClass = RTZArg;
   let PrintMethod = "printFRMArg";
-  let DecoderMethod = "decodeFRMArg";
+  let DecoderMethod = "decodeRTZArg";
 }
 
 //===----------------------------------------------------------------------===//