[llvm] [RISCV] Only disassemble fcvt.mod.w.d if the rounding mode is rtz. (PR #111308)
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Sun Oct 6 12:38:32 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
If we disassemble other rounding modes, we'll print something that can't be parsed.
---
Full diff: https://github.com/llvm/llvm-project/pull/111308.diff
2 Files Affected:
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+10)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td (+1-1)
``````````diff
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 7c8206cb44dec2..be0a61263297e4 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -375,6 +375,16 @@ static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
return MCDisassembler::Success;
}
+static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
+ const MCDisassembler *Decoder) {
+ assert(isUInt<3>(Imm) && "Invalid immediate");
+ if (Imm != RISCVFPRndMode::RTZ)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8cc5127f0e17a5..f62a7e1221122b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -47,7 +47,7 @@ def RTZArg : AsmOperandClass {
def rtzarg : Operand<XLenVT> {
let ParserMatchClass = RTZArg;
let PrintMethod = "printFRMArg";
- let DecoderMethod = "decodeFRMArg";
+ let DecoderMethod = "decodeRTZArg";
}
//===----------------------------------------------------------------------===//
``````````
</details>
https://github.com/llvm/llvm-project/pull/111308
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