[llvm] bea2803 - [CodeGen] Avoid repeated hash lookups (NFC) (#111274)

[via llvm-commits]

Author: Kazu Hirata
Date: 2024-10-06T09:21:25-07:00
New Revision: bea28037f6b68ee79b9360d91e0f3defd10fa976

URL: https://github.com/llvm/llvm-project/commit/bea28037f6b68ee79b9360d91e0f3defd10fa976
DIFF: https://github.com/llvm/llvm-project/commit/bea28037f6b68ee79b9360d91e0f3defd10fa976.diff

LOG: [CodeGen] Avoid repeated hash lookups (NFC) (#111274)

Added: 
    

Modified: 
    llvm/lib/CodeGen/RegisterBankInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/RegisterBankInfo.cpp b/llvm/lib/CodeGen/RegisterBankInfo.cpp
index 00dcc1fbcd0c77..e1720b038e2361 100644
--- a/llvm/lib/CodeGen/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterBankInfo.cpp
@@ -103,12 +103,10 @@ const TargetRegisterClass *
 RegisterBankInfo::getMinimalPhysRegClass(Register Reg,
                                          const TargetRegisterInfo &TRI) const {
   assert(Reg.isPhysical() && "Reg must be a physreg");
-  const auto &RegRCIt = PhysRegMinimalRCs.find(Reg);
-  if (RegRCIt != PhysRegMinimalRCs.end())
-    return RegRCIt->second;
-  const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClassLLT(Reg, LLT());
-  PhysRegMinimalRCs[Reg] = PhysRC;
-  return PhysRC;
+  const auto [RegRCIt, Inserted] = PhysRegMinimalRCs.try_emplace(Reg);
+  if (Inserted)
+    RegRCIt->second = TRI.getMinimalPhysRegClassLLT(Reg, LLT());
+  return RegRCIt->second;
 }
 
 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(