[llvm] Overhaul the TargetMachine and LLVMTargetMachine Classes (PR #111234)
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Fri Oct 4 23:12:34 PDT 2024
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git-clang-format --diff 1e75d08659aeb1aabf92b59f33649c414d4ff8b7 aa053ec7a677efae7339d71feea03e37e3327ca8 --extensions cpp,inc,h -- llvm/include/llvm/CodeGen/CodeGenCommonTMImpl.h llvm/include/llvm/CodeGen/MachineFunction.h llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h llvm/include/llvm/CodeGen/MachineModuleInfo.h llvm/include/llvm/CodeGen/RegisterUsageInfo.h llvm/include/llvm/CodeGen/ScheduleDAG.h llvm/include/llvm/CodeGen/TargetPassConfig.h llvm/include/llvm/Passes/CodeGenPassBuilder.h llvm/include/llvm/Target/TargetMachine.h llvm/lib/CodeGen/MIRParser/MIRParser.cpp llvm/lib/CodeGen/MachineFunction.cpp llvm/lib/CodeGen/MachineModuleInfo.cpp llvm/lib/CodeGen/RegUsageInfoCollector.cpp llvm/lib/CodeGen/RegisterUsageInfo.cpp llvm/lib/CodeGen/ResetMachineFunctionPass.cpp llvm/lib/CodeGen/TargetPassConfig.cpp llvm/lib/Target/AArch64/AArch64TargetMachine.cpp llvm/lib/Target/AArch64/AArch64TargetMachine.h llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h llvm/lib/Target/AMDGPU/R600TargetMachine.cpp llvm/lib/Target/ARC/ARCTargetMachine.cpp llvm/lib/Target/ARC/ARCTargetMachine.h llvm/lib/Target/ARM/ARMTargetMachine.cpp llvm/lib/Target/ARM/ARMTargetMachine.h llvm/lib/Target/AVR/AVRTargetMachine.cpp llvm/lib/Target/AVR/AVRTargetMachine.h llvm/lib/Target/BPF/BPFTargetMachine.cpp llvm/lib/Target/BPF/BPFTargetMachine.h llvm/lib/Target/CSKY/CSKYTargetMachine.cpp llvm/lib/Target/CSKY/CSKYTargetMachine.h llvm/lib/Target/DirectX/DirectXTargetMachine.cpp llvm/lib/Target/DirectX/DirectXTargetMachine.h llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp llvm/lib/Target/Hexagon/HexagonTargetMachine.h llvm/lib/Target/Lanai/LanaiTargetMachine.cpp llvm/lib/Target/Lanai/LanaiTargetMachine.h llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp llvm/lib/Target/LoongArch/LoongArchTargetMachine.h llvm/lib/Target/M68k/M68kTargetMachine.cpp llvm/lib/Target/M68k/M68kTargetMachine.h llvm/lib/Target/MSP430/MSP430TargetMachine.cpp llvm/lib/Target/MSP430/MSP430TargetMachine.h llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp llvm/lib/Target/Mips/MipsTargetMachine.cpp llvm/lib/Target/Mips/MipsTargetMachine.h llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp llvm/lib/Target/NVPTX/NVPTXTargetMachine.h llvm/lib/Target/PowerPC/PPCTargetMachine.cpp llvm/lib/Target/PowerPC/PPCTargetMachine.h llvm/lib/Target/RISCV/RISCVTargetMachine.cpp llvm/lib/Target/RISCV/RISCVTargetMachine.h llvm/lib/Target/SPIRV/SPIRVAPI.cpp llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp llvm/lib/Target/SPIRV/SPIRVTargetMachine.h llvm/lib/Target/Sparc/SparcTargetMachine.cpp llvm/lib/Target/Sparc/SparcTargetMachine.h llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp llvm/lib/Target/SystemZ/SystemZTargetMachine.h llvm/lib/Target/VE/VETargetMachine.cpp llvm/lib/Target/VE/VETargetMachine.h llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h llvm/lib/Target/X86/X86TargetMachine.cpp llvm/lib/Target/X86/X86TargetMachine.h llvm/lib/Target/XCore/XCoreTargetMachine.cpp llvm/lib/Target/XCore/XCoreTargetMachine.h llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp llvm/lib/Target/Xtensa/XtensaTargetMachine.h llvm/tools/llc/NewPMDriver.cpp llvm/tools/llc/llc.cpp llvm/tools/llvm-exegesis/lib/Assembler.cpp llvm/tools/llvm-exegesis/lib/Assembler.h llvm/tools/llvm-exegesis/lib/LlvmState.cpp llvm/tools/llvm-exegesis/lib/LlvmState.h llvm/tools/llvm-reduce/ReducerWorkItem.cpp llvm/tools/opt/optdriver.cpp llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp llvm/unittests/CodeGen/CCStateTest.cpp llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp llvm/unittests/CodeGen/GlobalISel/GISelMITest.h llvm/unittests/CodeGen/InstrRefLDVTest.cpp llvm/unittests/CodeGen/LexicalScopesTest.cpp llvm/unittests/CodeGen/MFCommon.inc llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp llvm/unittests/CodeGen/MachineBasicBlockTest.cpp llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp llvm/unittests/CodeGen/MachineInstrTest.cpp llvm/unittests/CodeGen/MachineOperandTest.cpp llvm/unittests/CodeGen/PassManagerTest.cpp llvm/unittests/CodeGen/RegAllocScoreTest.cpp llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp llvm/unittests/CodeGen/TargetOptionsTest.cpp llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp llvm/unittests/MI/LiveIntervalTest.cpp llvm/unittests/MIR/MachineMetadata.cpp llvm/unittests/MIR/MachineStableHashTest.cpp llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp llvm/unittests/Target/AArch64/InstSizes.cpp llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp llvm/unittests/Target/ARM/InstSizes.cpp llvm/unittests/Target/ARM/MachineInstrTest.cpp llvm/unittests/Target/LoongArch/InstSizes.cpp llvm/unittests/Target/VE/MachineInstrTest.cpp llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp llvm/unittests/Target/X86/MachineSizeOptsTest.cpp llvm/unittests/Target/X86/TernlogTest.cpp llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp offload/plugins-nextgen/common/src/JIT.cpp llvm/lib/CodeGen/CodeGenCommonTMImpl.cpp
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diff --git a/llvm/lib/CodeGen/CodeGenCommonTMImpl.cpp b/llvm/lib/CodeGen/CodeGenCommonTMImpl.cpp
index f001707b89..c06e651088 100644
--- a/llvm/lib/CodeGen/CodeGenCommonTMImpl.cpp
+++ b/llvm/lib/CodeGen/CodeGenCommonTMImpl.cpp
@@ -10,9 +10,9 @@
///
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
-#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
@@ -62,8 +62,8 @@ void CodeGenCommonTMImpl::initAsmInfo() {
// we'll crash later.
// Provide the user with a useful error message about what's wrong.
assert(TmpAsmInfo && "MCAsmInfo not initialized. "
- "Make sure you include the correct TargetSelect.h"
- "and that InitializeAllTargetMCs() is being invoked!");
+ "Make sure you include the correct TargetSelect.h"
+ "and that InitializeAllTargetMCs() is being invoked!");
if (Options.BinutilsVersion.first > 0)
TmpAsmInfo->setBinutilsVersion(Options.BinutilsVersion);
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 82d9cd8177..653820d5da 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -574,8 +574,7 @@ TargetPassConfig::getStartStopInfo(PassInstrumentationCallbacks &PIC) {
// Out of line constructor provides default values for pass options and
// registers all common codegen passes.
-TargetPassConfig::TargetPassConfig(TargetMachine &TM,
- PassManagerBase &PM)
+TargetPassConfig::TargetPassConfig(TargetMachine &TM, PassManagerBase &PM)
: ImmutablePass(ID), PM(&PM), TM(&TM) {
Impl = new PassConfigImpl();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index ad09b68daa..b35bcae135 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -993,7 +993,7 @@ namespace {
class GCNPassConfig final : public AMDGPUPassConfig {
public:
GCNPassConfig(TargetMachine &TM, PassManagerBase &PM)
- : AMDGPUPassConfig(TM, PM) {
+ : AMDGPUPassConfig(TM, PM) {
// It is necessary to know the register usage of the entire call graph. We
// allow calls without EnableAMDGPUFunctionCalls if they are marked
// noinline, so this is always required.
diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
index 039c8cfdad..94d101c610 100644
--- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -209,7 +209,7 @@ bool NVPTXAsmPrinter::lowerImageHandleOperand(const MachineInstr *MI,
void NVPTXAsmPrinter::lowerImageHandleSymbol(unsigned Index, MCOperand &MCOp) {
// Ewwww
- TargetMachine &TM = const_cast<TargetMachine&>(MF->getTarget());
+ TargetMachine &TM = const_cast<TargetMachine &>(MF->getTarget());
NVPTXTargetMachine &nvTM = static_cast<NVPTXTargetMachine&>(TM);
const NVPTXMachineFunctionInfo *MFI = MF->getInfo<NVPTXMachineFunctionInfo>();
const char *Sym = MFI->getImageHandleSymbol(Index);
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index da8c84410e..4d48491d30 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -356,9 +356,9 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: CodeGenCommonTMImpl(T, getDataLayoutString(TT), TT, CPU,
- computeFSAdditions(FS, OL, TT), Options,
- getEffectiveRelocModel(TT, RM),
- getEffectivePPCCodeModel(TT, CM, JIT), OL),
+ computeFSAdditions(FS, OL, TT), Options,
+ getEffectiveRelocModel(TT, RM),
+ getEffectivePPCCodeModel(TT, CM, JIT), OL),
TLOF(createTLOF(getTargetTriple())),
TargetABI(computeTargetABI(TT, Options)),
Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp
index 1be306bdb2..5b3369c070 100644
--- a/llvm/lib/Target/VE/VETargetMachine.cpp
+++ b/llvm/lib/Target/VE/VETargetMachine.cpp
@@ -90,8 +90,8 @@ VETargetMachine::VETargetMachine(const Target &T, const Triple &TT,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
: CodeGenCommonTMImpl(T, computeDataLayout(TT), TT, CPU, FS, Options,
- getEffectiveRelocModel(RM),
- getEffectiveCodeModel(CM, CodeModel::Small), OL),
+ getEffectiveRelocModel(RM),
+ getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(createTLOF()),
Subtarget(TT, std::string(CPU), std::string(FS), *this) {
initAsmInfo();
diff --git a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp
index 36972c2897..15d2baa24b 100644
--- a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp
@@ -66,8 +66,7 @@ body: |
.toNullTerminatedStringRef(S);
}
-std::unique_ptr<TargetMachine>
-AMDGPUGISelMITest::createTargetMachine() const {
+std::unique_ptr<TargetMachine> AMDGPUGISelMITest::createTargetMachine() const {
Triple TargetTriple("amdgcn-amd-amdhsa");
std::string Error;
const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
diff --git a/llvm/unittests/CodeGen/LexicalScopesTest.cpp b/llvm/unittests/CodeGen/LexicalScopesTest.cpp
index 16a8259df3..ea3bbdaa58 100644
--- a/llvm/unittests/CodeGen/LexicalScopesTest.cpp
+++ b/llvm/unittests/CodeGen/LexicalScopesTest.cpp
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/LexicalScopes.h"
+#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
diff --git a/llvm/unittests/CodeGen/MachineBasicBlockTest.cpp b/llvm/unittests/CodeGen/MachineBasicBlockTest.cpp
index 5e59856e3f..4e8abea787 100644
--- a/llvm/unittests/CodeGen/MachineBasicBlockTest.cpp
+++ b/llvm/unittests/CodeGen/MachineBasicBlockTest.cpp
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
diff --git a/llvm/unittests/CodeGen/MachineInstrTest.cpp b/llvm/unittests/CodeGen/MachineInstrTest.cpp
index 00159f7343..a0877d6a19 100644
--- a/llvm/unittests/CodeGen/MachineInstrTest.cpp
+++ b/llvm/unittests/CodeGen/MachineInstrTest.cpp
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp
index 7e870ded43..6db769efd0 100644
--- a/llvm/unittests/CodeGen/MachineOperandTest.cpp
+++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp
@@ -6,9 +6,9 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/ADT/ilist_node.h"
+#include "llvm/CodeGen/CodeGenCommonTMImpl.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp
index 4793491c6e..cd3307598d 100644
--- a/llvm/unittests/MI/LiveIntervalTest.cpp
+++ b/llvm/unittests/MI/LiveIntervalTest.cpp
@@ -57,8 +57,7 @@ std::unique_ptr<TargetMachine> createTargetMachine() {
std::unique_ptr<Module> parseMIR(LLVMContext &Context,
legacy::PassManagerBase &PM,
std::unique_ptr<MIRParser> &MIR,
- const TargetMachine &TM,
- StringRef MIRCode) {
+ const TargetMachine &TM, StringRef MIRCode) {
SMDiagnostic Diagnostic;
std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
MIR = createMIRParser(std::move(MBuffer), Context);
diff --git a/llvm/unittests/Target/LoongArch/InstSizes.cpp b/llvm/unittests/Target/LoongArch/InstSizes.cpp
index 05df7e0165..4a679707fc 100644
--- a/llvm/unittests/Target/LoongArch/InstSizes.cpp
+++ b/llvm/unittests/Target/LoongArch/InstSizes.cpp
@@ -42,8 +42,8 @@ std::unique_ptr<LoongArchInstrInfo> createInstrInfo(TargetMachine *TM) {
/// the \p InputMIRSnippet (global variables etc)
/// Inspired by AArch64
void runChecks(
- TargetMachine *TM, LoongArchInstrInfo *II,
- const StringRef InputIRSnippet, const StringRef InputMIRSnippet,
+ TargetMachine *TM, LoongArchInstrInfo *II, const StringRef InputIRSnippet,
+ const StringRef InputMIRSnippet,
std::function<void(LoongArchInstrInfo &, MachineFunction &)> Checks) {
LLVMContext Context;
``````````
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https://github.com/llvm/llvm-project/pull/111234
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