[llvm] Overhaul the TargetMachine and LLVMTargetMachine Classes (PR #111234)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 4 23:09:27 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Matin Raayai (matinraayai)
<details>
<summary>Changes</summary>
Following discussions in #<!-- -->110443, and the following earlier discussions in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html, https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine` interface classes. More specifically:
1. Makes `TargetMachine` the only class implemented under `TargetMachine.h` in the `Target` library.
2. `TargetMachine` contains target-specific interface functions that relate to IR/CodeGen/MC constructs, whereas before (at least on paper) it was supposed to have only IR/MC constructs. Any Target that doesn't want to use the independent code generator simply does not implement them, and returns either `false` or `nullptr`.
3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming aims to make the purpose of `LLVMTargetMachine` clearer. Its interface was moved under the CodeGen library, to further emphasis its usage in Targets that use CodeGen directly.
4. Makes `TargetMachine` the only interface used across LLVM and its projects. With these changes, `CodeGenCommonTMImpl` is simply a set of shared function implementations of `TargetMachine`, and CodeGen users don't need to static cast to `LLVMTargetMachine` every time they need a CodeGen-specific feature of the `TargetMachine`.
5. More importantly, does not change any requirements regarding library linking.
cc @<!-- -->arsenm @<!-- -->aeubanks
---
Patch is 147.27 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/111234.diff
120 Files Affected:
- (modified) llvm/docs/WritingAnLLVMBackend.rst (+9-9)
- (added) llvm/include/llvm/CodeGen/CodeGenCommonTMImpl.h (+92)
- (modified) llvm/include/llvm/CodeGen/MachineFunction.h (+4-4)
- (modified) llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h (+3-3)
- (modified) llvm/include/llvm/CodeGen/MachineModuleInfo.h (+7-8)
- (modified) llvm/include/llvm/CodeGen/RegisterUsageInfo.h (+3-3)
- (modified) llvm/include/llvm/CodeGen/ScheduleDAG.h (+2-2)
- (modified) llvm/include/llvm/CodeGen/TargetPassConfig.h (+5-5)
- (modified) llvm/include/llvm/Passes/CodeGenPassBuilder.h (+1-1)
- (modified) llvm/include/llvm/Target/TargetMachine.h (+19-71)
- (modified) llvm/lib/CodeGen/CMakeLists.txt (+1-1)
- (renamed) llvm/lib/CodeGen/CodeGenCommonTMImpl.cpp (+23-24)
- (modified) llvm/lib/CodeGen/MIRParser/MIRParser.cpp (+3-3)
- (modified) llvm/lib/CodeGen/MachineFunction.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MachineModuleInfo.cpp (+4-4)
- (modified) llvm/lib/CodeGen/RegUsageInfoCollector.cpp (+1-1)
- (modified) llvm/lib/CodeGen/RegisterUsageInfo.cpp (+1-1)
- (modified) llvm/lib/CodeGen/ResetMachineFunctionPass.cpp (+1-1)
- (modified) llvm/lib/CodeGen/TargetPassConfig.cpp (+6-4)
- (modified) llvm/lib/Passes/PassRegistry.def (+1-3)
- (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+5-5)
- (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.h (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+6-5)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h (+3-3)
- (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/ARC/ARCTargetMachine.cpp (+5-5)
- (modified) llvm/lib/Target/ARC/ARCTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/ARM/ARMTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/ARM/ARMTargetMachine.h (+2-1)
- (modified) llvm/lib/Target/AVR/AVRTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/AVR/AVRTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/BPF/BPFTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/BPF/BPFTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/DirectX/DirectXTargetMachine.cpp (+5-5)
- (modified) llvm/lib/Target/DirectX/DirectXTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/Lanai/LanaiTargetMachine.cpp (+4-4)
- (modified) llvm/lib/Target/Lanai/LanaiTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/M68k/M68kTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/M68k/M68kTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/MSP430/MSP430TargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/MSP430/MSP430TargetMachine.h (+2-2)
- (modified) llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp (+2-2)
- (modified) llvm/lib/Target/Mips/MipsTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/Mips/MipsTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp (+1-1)
- (modified) llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/NVPTX/NVPTXTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/SPIRV/SPIRVAPI.cpp (+2-3)
- (modified) llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/SPIRV/SPIRVTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/Sparc/SparcTargetMachine.cpp (+5-5)
- (modified) llvm/lib/Target/Sparc/SparcTargetMachine.h (+2-1)
- (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.h (+2-1)
- (modified) llvm/lib/Target/VE/VETargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/VE/VETargetMachine.h (+2-2)
- (modified) llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp (+3-3)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/X86/X86TargetMachine.cpp (+3-5)
- (modified) llvm/lib/Target/X86/X86TargetMachine.h (+2-2)
- (modified) llvm/lib/Target/XCore/XCoreTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/XCore/XCoreTargetMachine.h (+2-2)
- (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp (+3-3)
- (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.h (+2-2)
- (modified) llvm/tools/llc/NewPMDriver.cpp (+3-5)
- (modified) llvm/tools/llc/llc.cpp (+3-4)
- (modified) llvm/tools/llvm-exegesis/lib/Assembler.cpp (+3-5)
- (modified) llvm/tools/llvm-exegesis/lib/Assembler.h (+2-2)
- (modified) llvm/tools/llvm-exegesis/lib/LlvmState.cpp (+5-6)
- (modified) llvm/tools/llvm-exegesis/lib/LlvmState.h (+1-1)
- (modified) llvm/tools/llvm-reduce/ReducerWorkItem.cpp (+2-5)
- (modified) llvm/tools/opt/optdriver.cpp (+5-3)
- (modified) llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp (+3-3)
- (modified) llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp (+3-4)
- (modified) llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp (+6-6)
- (modified) llvm/unittests/CodeGen/CCStateTest.cpp (+1-1)
- (modified) llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp (+7-9)
- (modified) llvm/unittests/CodeGen/GlobalISel/GISelMITest.h (+6-6)
- (modified) llvm/unittests/CodeGen/InstrRefLDVTest.cpp (+4-4)
- (modified) llvm/unittests/CodeGen/LexicalScopesTest.cpp (+1-1)
- (modified) llvm/unittests/CodeGen/MFCommon.inc (+4-4)
- (modified) llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp (+1-1)
- (modified) llvm/unittests/CodeGen/MachineBasicBlockTest.cpp (+1-1)
- (modified) llvm/unittests/CodeGen/MachineDomTreeUpdaterTest.cpp (+1-2)
- (modified) llvm/unittests/CodeGen/MachineInstrTest.cpp (+1-1)
- (modified) llvm/unittests/CodeGen/MachineOperandTest.cpp (+1-1)
- (modified) llvm/unittests/CodeGen/PassManagerTest.cpp (+2-4)
- (modified) llvm/unittests/CodeGen/RegAllocScoreTest.cpp (+1-1)
- (modified) llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp (+3-3)
- (modified) llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp (+4-5)
- (modified) llvm/unittests/CodeGen/TargetOptionsTest.cpp (+1-2)
- (modified) llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp (+3-4)
- (modified) llvm/unittests/MI/LiveIntervalTest.cpp (+5-5)
- (modified) llvm/unittests/MIR/MachineMetadata.cpp (+3-4)
- (modified) llvm/unittests/MIR/MachineStableHashTest.cpp (+3-4)
- (modified) llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp (+4-4)
- (modified) llvm/unittests/Target/AArch64/InstSizes.cpp (+15-15)
- (modified) llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp (+4-4)
- (modified) llvm/unittests/Target/ARM/InstSizes.cpp (+3-3)
- (modified) llvm/unittests/Target/ARM/MachineInstrTest.cpp (+12-12)
- (modified) llvm/unittests/Target/LoongArch/InstSizes.cpp (+8-8)
- (modified) llvm/unittests/Target/VE/MachineInstrTest.cpp (+2-3)
- (modified) llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp (+5-5)
- (modified) llvm/unittests/Target/X86/MachineSizeOptsTest.cpp (+4-4)
- (modified) llvm/unittests/Target/X86/TernlogTest.cpp (+3-3)
- (modified) llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h (+2-3)
- (modified) llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp (+1-1)
- (modified) llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn (+1-1)
- (modified) offload/plugins-nextgen/common/src/JIT.cpp (+1-2)
``````````diff
diff --git a/llvm/docs/WritingAnLLVMBackend.rst b/llvm/docs/WritingAnLLVMBackend.rst
index f1f07e4681d509..ae4f635bc5ef87 100644
--- a/llvm/docs/WritingAnLLVMBackend.rst
+++ b/llvm/docs/WritingAnLLVMBackend.rst
@@ -152,7 +152,7 @@ To make your target actually do something, you need to implement a subclass of
``lib/Target/DummyTargetMachine.cpp``, but any file in the ``lib/Target``
directory will be built and should work. To use LLVM's target independent code
generator, you should do what all current machine backends do: create a
-subclass of ``LLVMTargetMachine``. (To create a target from scratch, create a
+subclass of ``CodeGenCommonTMImpl``. (To create a target from scratch, create a
subclass of ``TargetMachine``.)
To get LLVM to actually build and link your target, you need to run ``cmake``
@@ -165,15 +165,15 @@ located in the main ``CMakeLists.txt``.
Target Machine
==============
-``LLVMTargetMachine`` is designed as a base class for targets implemented with
-the LLVM target-independent code generator. The ``LLVMTargetMachine`` class
+``CodeGenCommonTMImpl`` is designed as a base class for targets implemented with
+the LLVM target-independent code generator. The ``CodeGenCommonTMImpl`` class
should be specialized by a concrete target class that implements the various
-virtual methods. ``LLVMTargetMachine`` is defined as a subclass of
-``TargetMachine`` in ``include/llvm/Target/TargetMachine.h``. The
-``TargetMachine`` class implementation (``TargetMachine.cpp``) also processes
-numerous command-line options.
+virtual methods. ``CodeGenCommonTMImpl`` is defined as a subclass of
+``TargetMachine`` in ``include/llvm/CodeGen/CodeGenCommonTMImpl.h``. The
+``TargetMachine`` class implementation (``include/llvm/Target/TargetMachine.cpp``)
+also processes numerous command-line options.
-To create a concrete target-specific subclass of ``LLVMTargetMachine``, start
+To create a concrete target-specific subclass of ``CodeGenCommonTMImpl``, start
by copying an existing ``TargetMachine`` class and header. You should name the
files that you create to reflect your specific target. For instance, for the
SPARC target, name the files ``SparcTargetMachine.h`` and
@@ -197,7 +197,7 @@ simply return a class member.
class Module;
- class SparcTargetMachine : public LLVMTargetMachine {
+ class SparcTargetMachine : public CodeGenCommonTMImpl {
const DataLayout DataLayout; // Calculates type size & alignment
SparcSubtarget Subtarget;
SparcInstrInfo InstrInfo;
diff --git a/llvm/include/llvm/CodeGen/CodeGenCommonTMImpl.h b/llvm/include/llvm/CodeGen/CodeGenCommonTMImpl.h
new file mode 100644
index 00000000000000..92bfc8f4f96d29
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/CodeGenCommonTMImpl.h
@@ -0,0 +1,92 @@
+//===-- CodeGenCommonTMImpl.h -----------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file This file describes the CodeGenCommonTMImpl class, which
+/// implements a set of functionality used by \c TargetMachine classes in
+/// LLVM that make use of the target-independent code generator.
+//===----------------------------------------------------------------------===//
+#ifndef LLVM_CODEGEN_CODEGENCOMMONTMIMPL_H
+#define LLVM_CODEGEN_CODEGENCOMMONTMIMPL_H
+#include "llvm/Target/TargetMachine.h"
+
+namespace llvm {
+
+/// \brief implements a set of functionality in the \c TargetMachine class
+/// for targets that make use of the independent code generator (CodeGen)
+/// library. Must not be used directly in code unless to inherit its
+/// implementation.
+class CodeGenCommonTMImpl : public TargetMachine {
+protected: // Can only create subclasses.
+ CodeGenCommonTMImpl(const Target &T, StringRef DataLayoutString,
+ const Triple &TT, StringRef CPU, StringRef FS,
+ const TargetOptions &Options, Reloc::Model RM,
+ CodeModel::Model CM, CodeGenOptLevel OL);
+
+ void initAsmInfo();
+
+public:
+ /// Get a TargetTransformInfo implementation for the target.
+ ///
+ /// The TTI returned uses the common code generator to answer queries about
+ /// the IR.
+ TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
+
+ /// Create a pass configuration object to be used by addPassToEmitX methods
+ /// for generating a pipeline of CodeGen passes.
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+
+ /// Add passes to the specified pass manager to get the specified file
+ /// emitted. Typically this will involve several steps of code generation.
+ /// \p MMIWP is an optional parameter that, if set to non-nullptr,
+ /// will be used to set the MachineModuloInfo for this PM.
+ bool
+ addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
+ raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
+ bool DisableVerify = true,
+ MachineModuleInfoWrapperPass *MMIWP = nullptr) override;
+
+ /// Add passes to the specified pass manager to get machine code emitted with
+ /// the MCJIT. This method returns true if machine code is not supported. It
+ /// fills the MCContext Ctx pointer which can be used to build custom
+ /// MCStreamer.
+ bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
+ raw_pwrite_stream &Out,
+ bool DisableVerify = true) override;
+
+ /// Adds an AsmPrinter pass to the pipeline that prints assembly or
+ /// machine code from the MI representation.
+ bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
+ raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
+ MCContext &Context) override;
+
+ Expected<std::unique_ptr<MCStreamer>>
+ createMCStreamer(raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
+ CodeGenFileType FileType, MCContext &Ctx) override;
+};
+
+/// Helper method for getting the code model, returning Default if
+/// CM does not have a value. The tiny and kernel models will produce
+/// an error, so targets that support them or require more complex codemodel
+/// selection logic should implement and call their own getEffectiveCodeModel.
+inline CodeModel::Model
+getEffectiveCodeModel(std::optional<CodeModel::Model> CM,
+ CodeModel::Model Default) {
+ if (CM) {
+ // By default, targets do not support the tiny and kernel models.
+ if (*CM == CodeModel::Tiny)
+ report_fatal_error("Target does not support the tiny CodeModel", false);
+ if (*CM == CodeModel::Kernel)
+ report_fatal_error("Target does not support the kernel CodeModel", false);
+ return *CM;
+ }
+ return Default;
+}
+
+} // namespace llvm
+
+#endif
\ No newline at end of file
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 053e7062fb4995..5a2b4881cfca2d 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -54,7 +54,7 @@ class DILocation;
class Function;
class GISelChangeObserver;
class GlobalValue;
-class LLVMTargetMachine;
+class TargetMachine;
class MachineConstantPool;
class MachineFrameInfo;
class MachineFunction;
@@ -256,7 +256,7 @@ struct LandingPadInfo {
class LLVM_ABI MachineFunction {
Function &F;
- const LLVMTargetMachine &Target;
+ const TargetMachine &Target;
const TargetSubtargetInfo *STI;
MCContext &Ctx;
@@ -634,7 +634,7 @@ class LLVM_ABI MachineFunction {
/// for instructions that have a stack spill fused into them.
const static unsigned int DebugOperandMemNumber;
- MachineFunction(Function &F, const LLVMTargetMachine &Target,
+ MachineFunction(Function &F, const TargetMachine &Target,
const TargetSubtargetInfo &STI, MCContext &Ctx,
unsigned FunctionNum);
MachineFunction(const MachineFunction &) = delete;
@@ -707,7 +707,7 @@ class LLVM_ABI MachineFunction {
void assignBeginEndSections();
/// getTarget - Return the target machine this machine code is compiled with
- const LLVMTargetMachine &getTarget() const { return Target; }
+ const TargetMachine &getTarget() const { return Target; }
/// getSubtarget - Return the subtarget for which this machine code is being
/// compiled.
diff --git a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h
index f54d455292da03..e194f4838e118c 100644
--- a/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h
+++ b/llvm/include/llvm/CodeGen/MachineFunctionAnalysis.h
@@ -18,7 +18,7 @@
namespace llvm {
class MachineFunction;
-class LLVMTargetMachine;
+class TargetMachine;
/// This analysis create MachineFunction for given Function.
/// To release the MachineFunction, users should invalidate it explicitly.
@@ -28,7 +28,7 @@ class MachineFunctionAnalysis
static AnalysisKey Key;
- const LLVMTargetMachine *TM;
+ const TargetMachine *TM;
public:
class Result {
@@ -41,7 +41,7 @@ class MachineFunctionAnalysis
FunctionAnalysisManager::Invalidator &);
};
- MachineFunctionAnalysis(const LLVMTargetMachine *TM) : TM(TM){};
+ MachineFunctionAnalysis(const TargetMachine *TM) : TM(TM) {};
Result run(Function &F, FunctionAnalysisManager &FAM);
};
diff --git a/llvm/include/llvm/CodeGen/MachineModuleInfo.h b/llvm/include/llvm/CodeGen/MachineModuleInfo.h
index 310cc4b2abb772..bec500dc609f32 100644
--- a/llvm/include/llvm/CodeGen/MachineModuleInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineModuleInfo.h
@@ -43,7 +43,7 @@
namespace llvm {
class Function;
-class LLVMTargetMachine;
+class TargetMachine;
class MachineFunction;
class Module;
@@ -83,7 +83,7 @@ class MachineModuleInfo {
friend class MachineModuleInfoWrapperPass;
friend class MachineModuleAnalysis;
- const LLVMTargetMachine &TM;
+ const TargetMachine &TM;
/// This is the MCContext used for the entire code generator.
MCContext Context;
@@ -109,10 +109,9 @@ class MachineModuleInfo {
MachineModuleInfo &operator=(MachineModuleInfo &&MMII) = delete;
public:
- explicit MachineModuleInfo(const LLVMTargetMachine *TM = nullptr);
+ explicit MachineModuleInfo(const TargetMachine *TM = nullptr);
- explicit MachineModuleInfo(const LLVMTargetMachine *TM,
- MCContext *ExtContext);
+ explicit MachineModuleInfo(const TargetMachine *TM, MCContext *ExtContext);
MachineModuleInfo(MachineModuleInfo &&MMII);
@@ -121,7 +120,7 @@ class MachineModuleInfo {
void initialize();
void finalize();
- const LLVMTargetMachine &getTarget() const { return TM; }
+ const TargetMachine &getTarget() const { return TM; }
const MCContext &getContext() const {
return ExternalContext ? *ExternalContext : Context;
@@ -173,9 +172,9 @@ class MachineModuleInfoWrapperPass : public ImmutablePass {
public:
static char ID; // Pass identification, replacement for typeid
- explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM = nullptr);
+ explicit MachineModuleInfoWrapperPass(const TargetMachine *TM = nullptr);
- explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM,
+ explicit MachineModuleInfoWrapperPass(const TargetMachine *TM,
MCContext *ExtContext);
// Initialization and Finalization
diff --git a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h
index aa1f5ef8110b0c..845ed09a852ad9 100644
--- a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h
+++ b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h
@@ -29,7 +29,7 @@
namespace llvm {
class Function;
-class LLVMTargetMachine;
+class TargetMachine;
class PhysicalRegisterUsageInfo : public ImmutablePass {
public:
@@ -41,7 +41,7 @@ class PhysicalRegisterUsageInfo : public ImmutablePass {
}
/// Set TargetMachine which is used to print analysis.
- void setTargetMachine(const LLVMTargetMachine &TM);
+ void setTargetMachine(const TargetMachine &TM);
bool doInitialization(Module &M) override;
@@ -63,7 +63,7 @@ class PhysicalRegisterUsageInfo : public ImmutablePass {
/// and 1 means content of register will be preserved around function call.
DenseMap<const Function *, std::vector<uint32_t>> RegMasks;
- const LLVMTargetMachine *TM = nullptr;
+ const TargetMachine *TM = nullptr;
};
} // end namespace llvm
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index 53265b286c7c87..54e65335edf3a2 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -32,7 +32,7 @@ namespace llvm {
template <class GraphType> struct GraphTraits;
template<class Graph> class GraphWriter;
-class LLVMTargetMachine;
+class TargetMachine;
class MachineFunction;
class MachineRegisterInfo;
class MCInstrDesc;
@@ -571,7 +571,7 @@ class TargetRegisterInfo;
class ScheduleDAG {
public:
- const LLVMTargetMachine &TM; ///< Target processor
+ const TargetMachine &TM; ///< Target processor
const TargetInstrInfo *TII; ///< Target instruction information
const TargetRegisterInfo *TRI; ///< Target processor register info
MachineFunction &MF; ///< Machine function
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 2f5951e3ec3bce..85f87de521855f 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -21,7 +21,7 @@
namespace llvm {
-class LLVMTargetMachine;
+class TargetMachine;
struct MachineSchedContext;
class PassConfigImpl;
class ScheduleDAGInstrs;
@@ -120,7 +120,7 @@ class TargetPassConfig : public ImmutablePass {
void setStartStopPasses();
protected:
- LLVMTargetMachine *TM;
+ TargetMachine *TM;
PassConfigImpl *Impl = nullptr; // Internal data structures
bool Initialized = false; // Flagged after all passes are configured.
@@ -148,7 +148,7 @@ class TargetPassConfig : public ImmutablePass {
bool addCoreISelPasses();
public:
- TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm);
+ TargetPassConfig(TargetMachine &TM, PassManagerBase &PM);
// Dummy constructor.
TargetPassConfig();
@@ -413,7 +413,7 @@ class TargetPassConfig : public ImmutablePass {
virtual void addFastRegAlloc();
/// addOptimizedRegAlloc - Add passes related to register allocation.
- /// LLVMTargetMachine provides standard regalloc passes for most targets.
+ /// CodeGenCommonTMImpl provides standard regalloc passes for most targets.
virtual void addOptimizedRegAlloc();
/// addPreRewrite - Add passes to the optimized register allocation pipeline
@@ -497,7 +497,7 @@ class TargetPassConfig : public ImmutablePass {
};
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
- LLVMTargetMachine &);
+ TargetMachine &);
} // end namespace llvm
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 13bc4700d87029..08629d656552d7 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -438,7 +438,7 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
Error addFastRegAlloc(AddMachinePass &) const;
/// addOptimizedRegAlloc - Add passes related to register allocation.
- /// LLVMTargetMachine provides standard regalloc passes for most targets.
+ /// CodeGenCommonTMImpl provides standard regalloc passes for most targets.
void addOptimizedRegAlloc(AddMachinePass &) const;
/// Add passes that optimize machine instructions after register allocation.
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index c3e9d41315f617..9bdb110bd36839 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -5,9 +5,9 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
-//
-// This file defines the TargetMachine and LLVMTargetMachine classes.
-//
+///
+/// This file defines the TargetMachine class.
+///
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_TARGETMACHINE_H
@@ -16,6 +16,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/PassManager.h"
+#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Error.h"
@@ -40,7 +41,6 @@ class MCAsmInfo;
class MCContext;
class MCInstrInfo;
class MCRegisterInfo;
-class MCStreamer;
class MCSubtargetInfo;
class MCSymbol;
class raw_pwrite_stream;
@@ -60,13 +60,13 @@ class TargetSubtargetInfo;
// The old pass manager infrastructure is hidden in a legacy namespace now.
namespace legacy {
class PassManagerBase;
-}
+} // namespace legacy
using legacy::PassManagerBase;
struct MachineFunctionInfo;
namespace yaml {
struct MachineFunctionInfo;
-}
+} // namespace yaml
//===----------------------------------------------------------------------===//
///
@@ -434,40 +434,12 @@ class TargetMachine {
function_ref<void(std::unique_ptr<Module> MPart)> ModuleCallback) {
return false;
}
-};
-
-/// This class describes a target machine that is implemented with the LLVM
-/// target-independent code generator.
-///
-class LLVMTargetMachine : public TargetMachine {
-protected: // Can only create subclasses.
- LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
- const Triple &TT, StringRef CPU, StringRef FS,
- const TargetOptions &Options, Reloc::Model RM,
- CodeModel::Model CM, CodeGenOptLevel OL);
-
- void initAsmInfo();
-
-public:
- /// Get a TargetTransformInfo implementation for the target.
- ///
- /// The TTI returned uses the common code generator to answer queries about
- /// the IR.
- TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
/// Create a pass configuration object to be used by addPassToEmitX methods
/// for generating a pipeline of CodeGen passes.
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
-
- /// Add passes to the specified pass manager to get the specified file
- /// emitted. Typically this will involve several steps of code generation.
- /// \p MMIWP is an optional parameter that, if set to non-nullptr,
- /// will be used to set the MachineModuloInfo for this PM.
- bool
- addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
- raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
- bool DisableVerify = true,
- MachineModuleInfoWrapperPass *MMIWP = nullptr) override;
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM) {
+ return nullptr;
+ }
virtual Error buildCodeGenPipeline(ModulePassManager &, raw_pwrite_stream &,
raw_pwrite_stream *, CodeGenFileType,
@@ -477,14 +449,6 @@ class LLVMTargetMachine : public TargetMachine {
inconvertibleErrorCode());
}
- /// Add passes to the specified pass manager to get machine code emitted with
- /// the MCJIT. This method returns true if machine code is not supported. It
- /// fills the MCContext Ctx pointer which can be used to build custom
- /// MCStreamer.
- bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
- raw_pwrite_stream &Out,
- bool DisableVerify = true) override;
-
/// Returns true if the target is expected to pass all machine verifier
/// checks. This is a stopgap measure to fix targets one by one. We will
/// remove this at some point and always enable the verifier when
@@ -493,13 +457,17 @@ class LLVMTargetMachine : public TargetMachine {
/// Adds an AsmPrinter pa...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/111234
More information about the llvm-commits
mailing list