[llvm] f873fc3 - [RISCV][GISEL] instruction-select vmclr (#110782)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 4 09:51:08 PDT 2024
Author: Michael Maitland
Date: 2024-10-04T12:51:04-04:00
New Revision: f873fc3ae2afb316d69c3f9be7b8903c18f217b0
URL: https://github.com/llvm/llvm-project/commit/f873fc3ae2afb316d69c3f9be7b8903c18f217b0
DIFF: https://github.com/llvm/llvm-project/commit/f873fc3ae2afb316d69c3f9be7b8903c18f217b0.diff
LOG: [RISCV][GISEL] instruction-select vmclr (#110782)
This is stacked on #110778. This PR adds and tests renderVLOp too, as
that is needed from vmclr.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/rvv/splat-vector.ll
Modified:
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/RISCVGISel.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4c2fcd38bd35ac..cfe8644b892298 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -100,6 +100,8 @@ class RISCVInstructionSelector : public InstructionSelector {
return selectSHXADD_UWOp(Root, ShAmt);
}
+ ComplexRendererFns renderVLOp(MachineOperand &Root) const;
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -376,6 +378,29 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
return std::nullopt;
}
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
+ assert(Root.isReg() && "Expected operand to be a Register");
+ MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
+
+ if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) {
+ auto C = RootDef->getOperand(1).getCImm();
+ if (C->getValue().isAllOnes())
+ // If the operand is a G_CONSTANT with value of all ones it is larger than
+ // VLMAX. We convert it to an immediate with value VLMaxSentinel. This is
+ // recognized specially by the vsetvli insertion pass.
+ return {{[=](MachineInstrBuilder &MIB) {
+ MIB.addImm(RISCV::VLMaxSentinel);
+ }}};
+
+ if (isUInt<5>(C->getZExtValue())) {
+ uint64_t ZExtC = C->getZExtValue();
+ return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(ZExtC); }}};
+ }
+ }
+ return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }}};
+}
+
InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
if (!Root.isReg())
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index a65577b9cacdae..0656928ca41f83 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -50,6 +50,14 @@ def GIAddrRegImm :
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
GIComplexPatternEquiv<AddrRegImm>;
+// FIXME: This is labelled as handling 's32', however the ComplexPattern it
+// refers to handles both i32 and i64 based on the HwMode. Currently this LLT
+// parameter appears to be ignored so this pattern works for both, however we
+// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
+// here.
+def GIVLOp : GIComplexOperandMatcher<s32, "renderVLOp">,
+ GIComplexPatternEquiv<VLOp>;
+
// Convert from i32 immediate to i64 target immediate to make SelectionDAG type
// checking happy so we can use ADDIW which expects an XLen immediate.
def as_i64imm : SDNodeXForm<imm, [{
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir
new file mode 100644
index 00000000000000..5600e351aa3987
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir
@@ -0,0 +1,76 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: negative_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: negative_vl
+ ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -2
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+---
+name: nonconst_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+ ; CHECK-LABEL: name: nonconst_vl
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = COPY $x10
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: nonzero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: nonzero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: zero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: zero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 0
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir
new file mode 100644
index 00000000000000..c2c0ed72be7b7c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir
@@ -0,0 +1,76 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: negative_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: negative_vl
+ ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -2
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+---
+name: nonconst_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+ ; CHECK-LABEL: name: nonconst_vl
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = COPY $x10
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: nonzero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: nonzero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: zero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: zero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 0
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
new file mode 100644
index 00000000000000..1ef1312cc17c0e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
@@ -0,0 +1,124 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: splat_zero_nxv1i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv1i1
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv2i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv2i1
+ ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 2 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv4i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv4i1
+ ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 4 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv8i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv8i1
+ ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 8 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv16i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv16i1
+ ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 16 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv32i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv32i1
+ ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 32 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv64i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv64i1
+ ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 64 x s1>)
+ PseudoRET implicit $v0
+
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
new file mode 100644
index 00000000000000..b7541cd4e96fb4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
@@ -0,0 +1,124 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: splat_zero_nxv1i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv1i1
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv2i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv2i1
+ ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 2 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv4i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv4i1
+ ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 4 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv8i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv8i1
+ ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 8 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv16i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv16i1
+ ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 16 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv32i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv32i1
+ ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 32 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv64i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv64i1
+ ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 64 x s1>)
+ PseudoRET implicit $v0
+
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/splat-vector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/splat-vector.ll
new file mode 100644
index 00000000000000..4e58c4dcec2d85
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/splat-vector.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -global-isel \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -global-isel \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
+
+define <vscale x 1 x i1> @splat_zero_nxv1i1() {
+; CHECK-LABEL: splat_zero_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 1 x i1> zeroinitializer
+}
+
+define <vscale x 2 x i1> @splat_zero_nxv2i1() {
+; CHECK-LABEL: splat_zero_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 2 x i1> zeroinitializer
+}
+
+define <vscale x 4 x i1> @splat_zero_nxv4i1() {
+; CHECK-LABEL: splat_zero_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 4 x i1> zeroinitializer
+}
+
+define <vscale x 8 x i1> @splat_zero_nxv8i1() {
+; CHECK-LABEL: splat_zero_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 8 x i1> zeroinitializer
+}
+
+define <vscale x 16 x i1> @splat_zero_nxv16i1() {
+; CHECK-LABEL: splat_zero_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 16 x i1> zeroinitializer
+}
+
+define <vscale x 32 x i1> @splat_zero_nxv32i1() {
+; CHECK-LABEL: splat_zero_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 32 x i1> zeroinitializer
+}
+
+define <vscale x 64 x i1> @splat_zero_nxv64i1() {
+; CHECK-LABEL: splat_zero_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ ret <vscale x 64 x i1> zeroinitializer
+}
+
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}
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