[llvm] [CodeGen] Use 128bits for LaneBitmask. (PR #111157)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> I think this is mostly because defining register tuples (2x, 3x and 4x) replicates the regunits. When I define the top bits and do some post-processing of the table in AArch64GenRegisterInfo.inc, I get the following lane masks:

This doesn't sound right. AMDGPU nearly exclusively uses register tuples, and we get one regunit per lane (well, one for each 16-bit half of each lane). 

https://github.com/llvm/llvm-project/pull/111157