[llvm] [RISCV][GISEL][NFC] Make MRI a member in RISCVInstructionSelector (PR #110926)

[Michael Maitland via llvm-commits]

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@@ -509,19 +495,19 @@ static void getOperandsForBranch(Register CondReg, MachineRegisterInfo &MRI,
 bool RISCVInstructionSelector::select(MachineInstr &MI) {
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
-  MachineRegisterInfo &MRI = MF.getRegInfo();
+  MRI = &MF.getRegInfo();
   MachineIRBuilder MIB(MI);
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michaelmaitland wrote:

Since it is unrelated, I will address this in a different PR. It looks like AArch64 creates a significant number of these MachineIRBuilders. And it looks like both RISC-V and AArch64 need to use it during instruction selection. Could you please tell me more about what you have in mind?

https://github.com/llvm/llvm-project/pull/110926